JZ2440 bare metal development and analysis: Memory controller 1 memory interface concept

JZ2440 internal structure:

The CPU writes values ​​to external registers, causing the external registers to emit different waveforms to control corresponding devices. From this, we will propose how different registers are selected inside the chip, so a memory controller is introduced inside the chip.

The CPU sends address information to the memory controller, and the memory controller selects different modules based on addr.

Memory devices

The memory interface (NOR FLASH, DM9000, SDRAM) is different. The CPU directly sends addresses and data to memory devices. There are many memory devices outside JZ2440. How to avoid interference? Each memory device has a chip select control terminal CS (chip select) to control which memory device is turned on. The signal of the chip select control terminal CS is managed by the memory controller. The CPU sends address information to the memory controller, and the memory controller sends a chip select signal according to the address.

If the address sent by the CPU is between 0x30000000 and 0x38000000, nGCS6 sends a low level, which selects each chip select signal of the SDRAM.

GPIO registers, UART registers, I2C registers, NAND control registers, memory devices (NOR FLASH; DM9000; SDRAM), etc. belong to the unified addressing of the CPU, while NAND FLASH is controlled by the NAND register and does not participate in the unified addressing. The NAND register controls the sending of the CS signal to the NAND FLASH.

Each chip select signal can select an address range of 2^27, requiring at least 27 address lines.

The CPU sends a 32-bit address to the memory controller, which: ① issues a chip select signal based on the address; ② extracts 27 bits to control peripherals