NRF24L01 module usage

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NRF24L01 module usage [Copy link]

NRF24L01 module usage

CE: module control line, when CSN is low, CE and CONFIG register jointly determine the state of NRF24L01CSN
: SPI chip select lineSCK
: SPI clock lineMOSI
: SPI data line (host output slave input)
MISO: SPI data line (host input slave output)
IRQ: interrupt signal line. It becomes low level when interrupted, and becomes low in the following three situations: Tx FIFO is sent and ACK is received (when ACK is enabled), Rx FIFO receives data, and the maximum number of retransmissions is reached.

2. SPI read and write timing

In the idle state, SCK is 0, CPOL=0; data is collected at the first clock transition edge, CPHA=0;

• Cn: SPI command bit
• Sn: STATUS register bit
• Dn: data bit (MSB, when transmitting multiple bytes, the low byte comes first)

3. Working mode

NRF24L01 working mode is controlled by PWR_UP (bit 1) and PRIM_RX (bit 0) of CE and CONFIG register (0x00):

1) Transceiver mode
There are three transceiver modes: Enhanced ShockBurstTM transceiver mode, ShockBurstTM transceiver mode and direct mode. The transceiver mode is determined by the device configuration word. When sending data in
the Enhanced ShockBurstTM transceiver mode
, the header and CRC check code are automatically added. In the sending mode, setting CE to high for at least 10us will enable the sending process; when receiving data, the header and CRC check code are automatically removed.
At the receiving end, the address is recorded after confirming that the data has been received, and a response signal is sent with this address as the target address. At the sending end, channel 0 is used to receive the response signal, so the receiving address of channel 0 is equal to the sending address end address to ensure that the correct response signal is received.
Enhanced ShockBurstTM sending process:

A. Send the address and data to be sent to NRF24L01 in sequence;
B. Configure the CONFIG register to put it into the sending mode;
C. MCU sets CE high (at least 10us) to stimulate Enhanced ShockBurstTM transmission;
D. Enhanced ShockBurstTM transmission: a) Power the RF front end;
b) Pack the RF data (add header, CRC checksum);
c) Transmit data packets at high speed;
d) Transmission is completed, NRF24L01 enters the idle state

Enhanced ShockBurstTM receiving process:

A. Configure the receiving address and the size of the data packet to be received;
B. Configure the CONFIG register to enter the receiving mode and set CE high;
C. After 130us, NRF24L01 enters the monitoring state and waits for the arrival of the data packet;
D. When the correct data packet (correct address and CRC check code) is received, NRF24L01 automatically removes the header, address and CRC check bit
E. NRF24L01 notifies the MCU by setting the RX_DR bit of the STATUS register (STATUS generally causes an MCU interrupt);
F. MCU reads the data from the FIFO (0x61 instruction);
G. After all data has been read, the STATUS register can be cleared; NRF24L01 can enter one of the four main modes.