SCI interrupt send

SCI is a full-duplex asynchronous serial communication interface, mainly used for communication between MCU and other computers or devices. Several independent MCUs can also realize serial communication through SCI to form a network. There are two SCIs (SCI0 and SCI1) in MC9S12XS128. To design an SCI serial communication program, you mainly need to master eight registers and set up initialization.

The following are SCI related registers:

SCIBDH, SCIBDL registers

IREN (infrared modulation mode enable bit) = 1, enable

= 0, disable

TNP[0:1]: Narrow pulse transmission bit

SBR[0:12]: Baud rate setting bit

When IREN = 1, SCI baud rate = SCI bus clock / (16 x SBR[12:0])

When IREN = 0, SCI baud rate = SCI bus clock / (32 x SBR[12:1])

SCIDRH, SCIDRL Registers

SCI has two data registers for transmission and reception, and their lower bits are accessed through SCIDRL. The read operation returns the content of the receive data register RDR, and the write operation data is placed in the transmit data register TDR. When M=1, that is, running in 9-bit data mode, SCIDRL and SCIDRH form a 9-bit SCI data word. At this time, SCIDRH must be written first so that it can enter the transmit shifter together with the lower byte (SCIDRL). If M=0, that is, SCI is only used for 7-bit or 8-bit data transmission, only SCIDRL can be accessed. When PE=1, that is, parity check is allowed, the parity bit is taken care of by hardware and no software intervention is required.

R8: Received bit 8, write operation to this bit is invalid. When SCI is set to 9-bit data operation mode, this bit is the 9th bit received from the serial data stream.

T8: Send bit 8, can be written at any time. When SCI is set to 9-bit data mode, this bit is sent to the 9th bit of the serial data stream. This bit does not need to be reset for each data, and can be reused each time it is sent.

R[0…7]T[0…7]: Receive/send data bits 7-0. A read operation returns the contents of the read-only register RDR, and a write operation writes to the write-only register TDR.

SCICR1 Register

LOOPS: In LOOP mode, the RXD pin is disconnected from the SCI receiving part, and the output of the transmitting part is connected to the receiving part internally. At this time, RXD can be used as a normal IO port, and TXD outputs the SCI signal.

= 1, LOOP mode is enabled

= 0, normal mode

SCISWAI: SCI stop bit in wait mode

= 1: Disable SCI in wait mode

= 0: Enable SCI in wait mode

RSRC: Receiver signal source selection bit. When LOOPS=1, RSRC determines the internal feedback signal path of the receiver.

= 1, the receiver input is connected to the TxD pin

= 0, the receiver input is internally connected to the transmitter output (not the TxD pin)

M: Mode selection bit (select character frame format)

= 1, 1 start bit, 8 data bits, 9th data bit, 1 stop bit

= 0, 1 start bit, 8 data bits, 1 stop bit

WAKE: Wake-up selection bit.

= 1, the address flag (the last data bit is 1) wakes up

= 0, medium idle wakeup

ILT: Idle detection mode selection bit. This bit selects one of the two idle detection modes that the SCI receiver can use.

= 1, conservative detection, SCI starts counting "1" after the stop bit, so the stop bit of the last byte and the previous "wide" bits have no effect on the detection time.

= 0, fast detection, SCI starts counting "1" immediately after the start bit of a frame, so the stop bit and any "1" before the stop bit are counted, so that the idle state can be detected early

PE: Parity enable bit.

= 1, parity check is enabled

= 0, disable parity check

PT: Odd/even check selection bit. If parity check is allowed, this bit determines whether the transceiver uses odd or even check.

= 1, select odd parity

= 0, select even parity

SCICR2 Register

TIE: Transmit Interrupt Enable Bit. When cleared to 0, TDRE is disabled from generating an interrupt. If set to 1, SCI interrupt requests are generated when TDRE is set to 1.

TCIE: Transmit end interrupt enable bit. When cleared to 0, TC is disabled to generate an interrupt. If set to 1, SCI interrupt request is generated when TC is set to 1.

RIE: Receive interrupt enable bit. When cleared to 0, RDRF and OR are disabled to generate interrupts. If set to 1, RDRF or OR is enabled to generate SCI interrupt requests when set to 1.

ILIE: Idle interrupt enable bit. When cleared to 0, it disables the IDLE interrupt. If set to 1, it allows the IDLE bit to generate an SCI interrupt request when it is set to 1.

TE: Transmit enable bit. When this bit is set from 0 to 1, it can be used to send an idle header.

= 1, the SCI transmit portion is enabled and the TxD pin (PS1/PS3) is used for transmission.

= 0, the transmitter is disabled

RE: Receive enable bit

= 1, enables the SCI receiver to operate.

= 0, the receiver is disabled

RWU: Receiver wake-up control bit

= 1, enables the wake-up function and disables the receiver interrupt. Normally, the hardware automatically clears this bit to wake up the receiver.

= 0, the SCI receiver operates normally

SBK: Break character transmission enable bit. As long as this bit remains 1, the transmitter will continuously send "0"; if it becomes 0, the TxD pin will become idle after the current full "0" frame is sent. If SBK is switched once, the transmitter will only send 10 (11) "0"s and then recover to the idle or data transmission state.

= 1, a stop character is generated, at least 10 or 11 consecutive "0"

= 0, the stop character generator is turned off

SCISR1 Register

TDRE: Send keeper empty flag. Before sending, you must read SCISR1 and confirm that TDRE=1.

After that, the new data is written into the send holder to start the sending process. This bit is 1 after reset

= 1, the data in the send holder has been transferred to the send shifter, and you can now write to the send holder.

New data

= 0, SC0DR is in busy state

TC: Transmit end flag. This bit is set when the transmitter is idle (no transmission action). Read SCISR1, then

Writing SCIDR afterwards will clear this bit

= 1, the transmitter is idle

= 0, the transmitter is busy

RDRF: Receive data ready flag. When the received character is ready in SCIDR, RDRF is set to 1.

Reading SCISR1 and SCIDR in sequence will automatically clear RDRF. After this bit is cleared, you must wait until RxD

The IDLE bit will be set to 1 again after the line becomes active and then becomes idle again.

= 1, data is ready in SCIDR

= 0, SCIDR is empty.

IDLE: Idle flag. Detects that the receiver RxD end is idle (receives 10 or more consecutive

When the RWU bit is 1, the idle state will not set this bit to 1. After this bit is cleared, you must wait for

The IDLE bit will not be set again until RDRF is set (the RxD line becomes active and then becomes idle again).

= 1, the RxD line is idle

= 0, RxD line is active

OR: Overlap error flag. If the data in the receive data register has not been read (RDRF = 1), the receive shift register

If the bit register is about to transmit new data to it, it is called an overlap error and the bit is set to 1. This bit must be cleared.

bit to allow new data to enter the receive data register

= 1, an overlap error occurs

= 0, no overlap

NF: Noise error flag. When a noise error occurs, this bit and RDRF are set in the same cycle, but

If an overlap error occurs or has occurred, this bit is not set.

=1, noise is detected during the reception of the start bit, data bit, or stop bit

= 0, the sampling results are consistent

FE: Frame format error. If a 0 is detected when a stop bit should appear, this bit is set.

Reading registers SCISRl and SCIDR will clear the FE flag

= 1, a 0 is detected when a stop bit is expected

= 0, a stop bit is detected

PF: Parity error flag. Indicates whether the parity of the received data is consistent with the check bit. Parity check allows

The required parity is determined by the PT bit in SC0CR1.

= 1, parity error

= 0, parity check is correct

SCISR2 Register

AMAP: Alternative Map This bit allows access to control registers that share the same address space. In a reset condition the SCI behaves the same as the previous version. AMAP = 1 allows access to an alternative set of control and status registers and hides the baud rate and SCI control registers

TXPOL: Transmit Polarity This bit controls the polarity of the transmitted data. In the NRZ format, a yes represents a mark and a zero represents a space for positive polarity, and the opposite polarity is the opposite. In the IrDA format, a zero is represented by a short high pulse in the middle of the bit time and the rest is a normal idle low, a short low pulse in the middle of the bit time for an idle high bit and the rest is a normal idle low, and a zero polarity is represented by an inverted polarity.

= 1, the polarity is opposite

= 0, normal mode

RXPOL: Receive polarity

= 1, the polarity is opposite

= 0, normal mode

BRK13: The length of the break character is controlled

= 1, the length of the stop character is 13 or 14 bits

= 0, the length of the stop character is 10 or 11 bits

TXDIR: Transmit pin data direction control bit in single-line mode

= 1, the TxD pin is used for output in single-line mode

= 0, the TxD pin is used to input in single-line mode

RAF: Receiver activity flag. Indicates whether the receiver is active.

During this period, this bit is set to 1 when the receiver detects an idle state or a false start bit (usually due to noise).

This bit is cleared to 0 when a sound or baud rate match error occurs. This bit is controlled by the receiver front end.

The following is the complete code for SCI interrupt sending:

#include            

#include "derivative.h"      

#define LED PORTB_PB0 //Define the data register of PORTB_PB0 port connected to the light-emitting diode

                              //The device is an LED, write '0' to light it up, write '1' to turn it off

#define LED_dir DDRB_DDRB0 //Define the direction register of PORTB_PB0 port connected to the light-emitting diode

                              //For LED_dir, write '0' for input and '1' for output

#define LED_ON 0 //LED turns on

#define LED_OFF 1 //LED turns off

#define BUS_CLOCK 32000000 //Bus frequency

#define OSC_CLOCK 16000000 //Crystal oscillator frequency