Embedded Learning Notes 2: Introduction to the 210 Power-on Startup Process

Memory:
SRAM static memory (on-chip RAM) has the characteristics of small capacity and high price, and the advantage is that it can be used directly after power-on without software initialization

DRAM dynamic memory (DDR2DDR3) is characterized by large capacity and low price. Its disadvantage is that it cannot be used directly after power-on and needs to be initialized by software.
In single-chip microcomputers: small memory requirements and the desire to develop as simply as possible, suitable for all SRAM
Embedded systems: large memory requirements and no bootable media such as NorFlash
PCs: large memory requirements and complex software, do not care about the initialization overhead of DRAM, suitable for all DRAM

External memory:
NorFlash: It is characterized by small capacity and high price. Its advantage is that it can be directly connected to the CPU via bus and can be read directly after the CPU is powered on, so it is generally used as a boot medium.

NandFlash (same as hard disk): Features: large capacity, low price, but not bus-accessible, that is, it cannot be directly read by the CPU after power-on. The CPU needs to run some initialization software first, and then read and write through the timing interface. (EMMC)

So the general PC is: small capacity BIOS (NorFlash) + large capacity hard disk (similar to NandFlash) + large capacity DRAM.
General single chip computer: small capacity NorFlash + small capacity SRAM.
Embedded system: Because NorFlash is very expensive, many embedded systems now tend not to use NorFlash.

Direct use: external large-capacity Nand + external large-capacity DRAM + SoC built-in SRAM

            
The booting method used by S5PV210 is: external large-capacity Nand + external large-capacity DRAM + SoC built-in SRAM.
In fact, the booting of 210 is even more interesting. 210 has a built-in 96KB SRAM (called iRAM) and a built-in 64KB NorFlash (called iROM). The booting process of 210 is roughly as follows:

Step 1: After the CPU is powered on, it reads the preset code (BL0) from the internal IROM and executes it. This IROM code first does some basic initialization (CPU clock, turn off the watchdog...) (This IROM code is set by Samsung before leaving the factory, and Samsung does not know what kind of DRAM will be connected to our board in the future, so this IROM cannot be responsible for initializing the external DRAM, so this code can only initialize things inside the SoC); then this code will determine the boot mode we choose (we can change the boot mode of the board through hardware jumpers), and then read the first part of the boot code (BL1, size is 16KB) from the corresponding external memory to the internal SRAM.

Step 2: Run BL1 (16KB) just read from the previous step from IRAM and then execute. BL1 is responsible for initializing NandFlash, then reading BL2 into IRAM (the remaining 80KB) and then running

Step 3: Run BL2 from IRAM, BL2 initializes DRAM, then reads OS into DRAM, then starts OS, and the boot process ends.

What did BL0 do?

Turn off the watchdog

Initialize instruction cache

Initialize the stack

Initializing the heap

Initialize the block device copy function device copy function

Setting up the SoC clock system

Copy BL1 to internal IRAM (16KB)

Check the checksum of BL1 and jump to BL1 to execute

Idea: Because the size of the boot code (uboot) is not fixed, some companies may only need 96kb, while others may not even need 1MB. Therefore, the two-step boot method mentioned above is not suitable. Samsung's solution is to divide the boot code into two halves (BL1 and BL2), and these two parts work together to complete the boot.

All startup of S5PV210

First start 1st and select the boot medium through OMpin

Then 2nd boot, from SD2

Restart Uart  

Reboot from USB