tq210 memory configuration

S5PV210 has two independent DRAM controllers, DMC0 and DMC1. DMC0 supports up to 512MByte and DMC1 supports up to 1GByte. Both DMC0 and DMC1 support two chip selects, CS0 and CS1. The memory module of S5PV210 is more complicated than that of 2440 and 6410. To correctly configure the memory of S5PV210, you should carefully read the relevant part of the chip manual. When configuring the parameters, you should also read the manual of the memory chip appropriately. The registers and configuration process of this part are more complicated (but not difficult). I will only briefly talk about the problems I encountered during the configuration.

1. Wiring principle

My development board is TQ210, and there are 8 128M*8bits memory chips on the development board. As you can see from the schematic diagram, 4 of them are connected in parallel to DMC0, and the other four are connected in parallel to DMC1. Here I only post one connection method, because all 8 chips are the same, except that the first four and the last four are mounted in different positions.

We can notice that TQ210 connects the address lines of four K4T1G084QQ in parallel and the data lines in series, which is exactly 32-bit data. In addition, we can also see that K4T1G084QQ only connects 14 address lines, because K4T1G084QQ has 14 row addresses and 10 column addresses, and these 14 lines are multiplexed. However, K4T1G084QQ has 8 banks, while DMC has only two bank lines. For this reason, S5PV210 provides the following solutions:

According to Note 3, we can see that when S5PV210 mounts 8bank memory, CS1 is reused as BANK2. In this state, S5PV210 is equivalent to having only one chip select pin CS0. This is understandable. We can also know from here that the num_chip parameter can be set to 1 (it has been tested that it can also be set to 2, but the configuration of MEMCONFIG1 is meaningless because there is only CS0 but no CS1 for 8bank). There is also a solution for memory chips with 8banks and 15 row addresses, so be sure to pay attention to the following notes. I didn't read the manual carefully enough when configuring it, and didn't read the following notes. As a result, I was stuck for a whole morning. I didn't understand the wiring principle of the memory chip, and even thought that the development board was connected incorrectly.

Two address mapping

There is an important difference between the DMC of S5PV210 and the DMC of 6410 and 2440. S5PV210 can control the memory address mapping. The address space of DMC0 is 0x2000,0000~0x3fff,ffff, and the address space of DMC1 is 0x4000,0000~0x7fff,ffff. DMC can map the memory chip to the appropriate location in its memory segment by configuring the register. This configuration is in the MEMCONFIG register. This address mapping made me entangled for a long time, and finally I looked up the information to understand it.

If you set chip_base to 0x20:

(1) The memory we mount is 128M, so the chip_mask should be set to 0xF8

(2) When we mount 256M memory, chip_mask should be set to 0xF0

(3) When we mount 512M, chip_mask should be set to 0xE0

(4) When we mount 1GB memory, chip_mask should be set to 0xC0.

Taking DMC0 as an example, when DMC0 receives an address from 0x2000,0000 to 0x3fff,ffff from AXI, it will do the following:

(1) The high 8 bits of the AXI address are ANDed with chip_mask to obtain the result, which is recorded as X.

(2) Compare X with the chip_base of MEMCONFIG0 and MEMCONFIG1 respectively. If they are equal, turn on the corresponding chip select.

If the mounted memory is 128M, and one chip is mounted on CS0 and CS1 respectively, then 128M=128*1024*1024=0x8000000, then the offset range of 128M memory should be 0x0000,0000~0x07ff,ffff, with 5 bits remaining in the high position. Then, we set the chip_base of MEMCONFIG0 to 0x20 and the chip_mask to 0xF8. In order to keep the memory continuous, we need to set the chip_base of MEMCONFIG1 to 0x28 and the chip_mask to 0xF8. When the address sent by AXI is 0x23xx,xxxx, 0x23&0xF8 gets 0x20, so the chip select CS0 will be turned on. When the address sent by AXI is 0x28xx,xxxx, 0x28&0xF8 gets 0x28, so the chip select CS1 will be turned on, and so on.

In particular, when the memory chip loaded is 8bank (8bank memory chip generally has 14/15 row addresses and 10 column addresses, that is, the capacity is generally 512M or 1G), since CS1 is the bank2 pin, in order to keep the CS0 clock in the chip select state, for 512M memory, chip_mask needs to be set to 0xE0. This is because 512M=512*1024*1024=0x2000,0000, that is, the offset of 512M memory should be 0x0000,0000~0x1fff,ffff, so the high bit remains 3 bits, that is, 0xE0. Of course, if the memory is 1G=1024*1024*1024=0x4000,0000, that is, the offset is 0x0000,0000~0x3fff,ffff, and the high bit remains 2, so set chip_mask to 0xC0. In this way, the offset of these two values ​​will be calculated.

Three configuration processes

The configuration of memory chips is relatively complicated. Fortunately, the chip manual provides the initialization sequence of common memory types. The memory of TQ210 is DDR2, which can be initialized in the following order:

1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.   

2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock frequency. Set the PhyControl0.ctrl_dll_on bit-field to '1' to turn on the PHY DLL.   

3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value according to clock frequency and memory tAC parameters.   

4. Set the PhyControl0.ctrl_start bit-field to '1'.     

5. Set the ConControl. At this moment, an auto refresh counter should be off.     

6. Set the MemControl. At this moment, all power down modes should be off.   

7. Set the MemConfig0 register. If there are two external memory chips, set the MemConfig1 register.   

8. Set the PrechConfig and PwrdnConfig registers.   

9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.   

10. If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.   

11. Wait for the PhyStatus0.ctrl_locked bit-fields to change to '1'. Check whether PHY DLL is locked.   

12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT) variation during memory operation. Therefore, PHY DLL should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according to the PhyStatus0.ctrl_lock_value[9:2] bit-field to fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.   

13. Confirm whether stable clock is issued minimum 200us after power on   

14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level  

15. Wait for minimum 400ns.   

16. Issue a PALL command using the DirectCmd register.   

17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.   

18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.   

19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.   

20. Issue a MRS command using the DirectCmd register to reset the memory DLL.   

21. Issue a PALL command using the DirectCmd register.   

22. Issue two Auto Refresh commands using the DirectCmd register.   

23. Issue a MRS command using the DirectCmd register to program the operating parameters without resetting the memory DLL.   

24. Wait for minimum 200 clock cycles.   

25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS command to exit OCD Calibration Mode and to program the operating parameters.   

26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.   

27. Set the ConControl to turn on an auto refresh counter. 28. If power down modes is required, set the MemControl registers.

The above is the initialization sequence of the DDR2 memory chip given in the manual, but it may be difficult to configure simply according to the above steps. At this time, we can refer to the memory initialization code of u-boot to initialize the memory. In the end, you will find that the operation sequence of u-boot is exactly the same as above.

Four memory initialization codes

I uploaded my memory configuration code to the CSDN download space. If necessary, you can download it from my resources. It is the C language version.

Five remaining issues

The memory configuration code is burned to Nand and runs normally, but it is abnormal when booted via USB. The reason has not been found yet. If anyone has solved it or has other questions, please leave a message to tell me. Thank you in advance.

Now we have found the reason. It turns out that the USB boot process of S5PV210 is different from the Nand boot process. When S5PV210 is booted in USB mode, it will first download a firmware program provided by Samsung to 0xd0020010 and run it. Then, it will download the user code to 0x23e00000 and run it. In other words, the firmware program completes the memory initialization because our code is located at 0x23e00000. When our code configures the memory again, the memory will be reset, and the code downloaded to the memory will be lost, so the program will hang when it executes the memory initialization function.

To prove the above hypothesis, I added a program to the code, which copies the code in the memory to the position after 16K of iram (there is a problem if it is copied directly to 0xd0020000, I copied it to 0xd0024000, and I don’t know why yet), and then jumps the code to IRAM. If the code can run normally, it can prove that the memory initialization part is normal. The experimental results are positive. The following is a summary: