MICRO2440 Interrupt Learning

The interrupt controller in S3C2440A accepts requests from 60 interrupt sources, some of which have sub-interrupt sources attached, and they share one interrupt source. There are two types of interrupts: IRQ interrupts and FIQ interrupts. Each interrupt can be set to IRQ or FIQ. The IRQ interrupt also needs to be determined by the priority judge. The interrupt process: Take the interrupt with a sub-interrupt source as an example: If the interrupt with a sub-interrupt source is interrupted, the corresponding bit of the sub-interrupt source request register (SUBSRCPND) is set to 1, which indicates which sub-interrupt source is the interrupt. Then see if the interrupt is masked. The mask is set by the sub-interrupt mask register (SUBMASK), and then the source interrupt request register (SRCPND) is set to 1 accordingly. This bit indicates which interrupt source is the interrupt. Then see if the interrupt is masked, which is set by the interrupt mask register (MASK). Then see if the interrupt is set to IRQ or FIQ, which is set by the interrupt mode register (MODE). For IRQ interrupts, its priority must be considered, which is set by the priority register. Finally, the interrupt with the highest priority is obtained. In the final interrupt request register (INTPND), the corresponding bit is set to 1, and finally waits for the CPU to respond to the interrupt. Interrupt clearing order: first clear SUBSRCPND, then SRCPND, and finally INTPND. To clear the flag bit, just write 1 to the corresponding bit. Interrupt priority Each arbiter's 1-bit arbiter mode control (ARB_MODE) and 2-bit selection control signal (ARB_SEL) control priority as follows: – If the ARB_SEL bit is 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. – If the ARB_SEL bit is 01b, the priority order is REQ0, REQ2, REQ3, REQ4, REQ1, and REQ5. – If the ARB_SEL bit is 10b, the priority order is REQ0, REQ3, REQ4, REQ1, REQ2, and REQ5. – If the ARB_SEL bit is 11b, the priority order is REQ0, REQ4, REQ1, REQ2, REQ3, and REQ5. REQ0 always has the highest priority and REQ5 always has the lowest priority. By changing the ARB_SEL bits, the order of REQ1 to REQ4 can be rotated. If the ARB_MODE bit is set to 0, the ARB_SEL bits cannot be changed automatically, which makes the arbiter operate in fixed priority mode. If ARB_MODE 1, the ARB_SEL bits are changed in a rotating manner, for example, if REQ1 is serviced, the ARB_SEL bits are automatically changed to 01b so that REQ1 enters the lowest priority. The detailed results of the ARB_SEL change are as follows: – If REQ0 or REQ5 is serviced, the ARB_SEL bits are not changed – If REQ1 is serviced, the ARB_SEL bits are changed to 01b. – If REQ2 is serviced, the ARB_SEL bits are changed to 10b. – If REQ3 is serviced, the ARB_SEL bits are changed to 11b. – If REQ4 is serviced, the ARB_SEL bits are changed to 00b. IRQ type interrupt priority, FIQ does not exist, from top to bottom, the priority decreases in turnInterrupt vector: #define _RAM_STARTADDRESS 0x30000000 #define _ISR_STARTADDRESS 0x33ffff00 #define _MMUTT_STARTADDRESS 0x33ff8000 #define _STACK_BASEADDRESS 0x33ff8000 #define HEAPEND 0x33ff0000 #define _NONCACHE_STARTADDRESS 0x31000000 #define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0)) #define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4)) #define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8)) #define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0x8)) #define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10)) #define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14)) #define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18)) #define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c)) #define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20)) #define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24)) #define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x26)) #define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c)) #define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30)) #define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34)) #define pISR_CAM (*(unsigned *)(_ISR_STARTADDRESS+0x38)) #define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3c)) #define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40)) #define pISR_WDT_AC97 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) #define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48)) #define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c)) #define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50)) #define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54)) #define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58)) #define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5c)) #define pISR_LCD (*(unsigned *)(_ISR_STARTADDRESS+0x5c)) #define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64)) #define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68)) #define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c)) #define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70)) #define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74)) #define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78)) #define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7c)) #define pISR_NFCON (*(unsigned *)(_ISR_STARTADDRESS+0x80))#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0x9c))//interrupt handler, marked with __irq

void __irq IicISR(void)

{

       rSRCPND |= 0x1<<27;

       rINTPND |= 0x1<<27;

       flag = 0; // clear flag

}

//Parallel connection between interrupt handler and interrupt source

pISR_UART0 = (U32)uartISR;

       pISR_IIC = (U32)IicISR;

1. Which vector addresses are allocated by the system by default?

A, of course the first is reset, the reset program disables the watchdog, and sets the SP position of each interrupt mode

Note: To call a C function, you must first set up the stack, such as the main function.

B, several other interrupt vector entry addresses. When a corresponding interrupt occurs, the system automatically jumps to the corresponding entry address.

2. Interrupt handler:

a) Calculate the return address

b) Protect the scene and push it into the stack of that mode

c) Interrupt handling

d) Clear the interrupt flag

e) Restoration of the scene

f) Interrupt return

.global _start

_start:    

    b Reset

HandleUndef:

    b HandleUndef

 HandleSWI:

    b HandleSWI

HandlePrefetchAbort:

    b HandlePrefetchAbort

HandleDataAbort:

    b HandleDataAbort

HandleNotUsed:

b HandleNotUsed

HandleIRQ:

    b HandleIRQ

HandleFIQ:

    b HandleFIQ

Reset:                 

    ldr sp, =4096 @ Set the stack pointer, because the following are all C functions bl disable_watch_dog @ Disable the watchdog, otherwise the CPU will restart continuously

    msr cpsr_c, #0xd2 @ Enter interrupt mode

    ldr sp, =3072 @ Set interrupt mode stack pointer

    msr cpsr_c, #0xd3 @ Enter management mode

    ldr sp, =4096 @ Set the management mode stack pointer,

                       @ In fact, after reset, the CPU is in management mode.

    bl init_led @ Initialize the GPIO pin of LED

    bl init_irq @ Call interrupt initialization function in init.c

    msr cpsr_c, #0x53 @ Set I-bit = 0, enable IRQ interrupt

    ldr lr, =halt_loop @ Set the return address

    ldr pc, =main @ Call main function

halt_loop:

    b halt_loop

HandleIRQ:

    sub lr, lr, #4 @ Calculate the return address

    stmdb sp!, { r0-r12,lr } @ Save the used registers

                             @ Note that the sp at this time is the sp in interrupt mode

@ The initial value is 3072 set above

    ldr lr, =int_return @ Set the return address of calling EINT_Handle function 

    ldr pc, =EINT_Handle @ Call the interrupt service function in interrupt.c

int_return:

    ldmia sp!, { r0-r12,pc }^ @ interrupt return, ^ means copy the value of spsr to cpsr

void EINT_Handle()

{

    unsigned long oft = INTOFFSET;

    unsigned long val;

    switch( oft )

    {

        // S2 is pressed

        case 0:

                 case1:

                      . . . . .

}

    // Clear interrupt

    if( oft == 5 )

        EINTPEND = (1<<11); // EINT8_23 shares IRQ5

    SRCPND = 1<    INTPND = 1<}