Why can't STM8's PWM be output using TIM1, but TIM2 can? The following program code is written for TIM1's PWM output.
STM8S series microcontroller
PC1 pin is used to control the PWM output, namely TIM1_CH1 channel
PC2 pin is used to control the PWM output, namely TIM1_CH2 channel
PC3 pin is used to control the PWM output, namely TIM1_CH3 channel
//PWM initialization
void Driver_PWMON(u8 ch,u8 Num)
{
//Open TIM1 clock
CLK->PCKENR1 |= CLK_PCKENR1_TIM1;
//Set PWM frequency, Fpwm=Fmaster/TIM2_ARR
//Here Fpwm = 2000000/100 = 20K
TIM1->ARRH = 0;
TIM1->ARRL = 100;
//Start counting and start PWM output
TIM1->BKR |= TIM1_BKR_MOE;
switch(ch)
{
case 1:
TIM1->CCMR1 |= 0x70; //Set TIM1_CH1 to PWM mode 2, effective level is high
pwm_ch_on(1); //Turn on TIM1_CH1 channel output
TIM1->CCR1H = 0; // Initialize PWM channel duty cycle 1:1
TIM1->CCR1L = Num;
break;
case 2:
TIM1->CCMR2 |= 0x70; //Set TIM1_CH2 to PWM mode 2, effective level is high
pwm_ch_on(2); //Turn on TIM1_CH1 channel output
TIM1->CCR2H = 0; // Initialize PWM channel duty cycle 1:1
TIM1->CCR2L = Num;
break;
case 3:
TIM1->CCMR3 |= 0x70; //Set TIM1_CH3 to PWM mode 2, effective level is high
pwm_ch_on(3); //Turn on TIM1_CH1 channel output
TIM1->CCR3H = 0; // Initialize PWM channel duty cycle 1:1
TIM1->CCR3L = Num;
break;
case 4:
TIM1->CCMR4 |= 0x70; //Set TIM1_CH4 to PWM mode 2, effective level is high
pwm_ch_on(4); //Turn on TIM1_CH1 channel output
TIM1->CCR4H = 0; // Initialize PWM channel duty cycle 1:1
TIM1->CCR4L = Num;
break;
}
TIM1->CR1 |= TIM1_CR1_CEN;
}
//PWM duty cycle adjustment 0-100
void Driver_PWMSet(u8 ch,u8 Num)
{
if(Num > 100)
return;
switch(ch)
{
case 1:
TIM1->CCR1L = Num;
break;
case 2:
TIM1->CCR2L = Num;
break;
case 3:
TIM1->CCR3L = Num;
break;
case 4:
TIM1->CCR4L = Num;
break;
}
}
//Open the PWM channel
void pwm_ch_on(u8 ch)
{
switch(ch)
{
case 1:
TIM1->CCER1 |= 0x01;
break;
case 2:
TIM1->CCER1 |= 0x10;
break;
case 3:
TIM1->CCER2 |= 0x01;
break;
case 4:
TIM1->CCER2 |= 0x10;
break;
}
}
//Close the PWM channel
void pwm_ch_close(u8 ch)
{
switch(ch)
{
case 1:
TIM1->CCER1 &= ~0x01;
break;
case 2:
TIM1->CCER1 &= ~0x10;
break;
case 3:
TIM1->CCER2 &= ~0x01;
break;
case 4:
TIM1->CCER2 &= ~0x10;
break;
}
}
//Run the main function
int main(void)
{
Driver_PWMON(1,0);
Driver_PWMON(2,0);
Driver_PWMON(3,0);
while(1)
{
u8 a= 0,b=0;
for(b=1; b<4; b++)
{
for(a=1;a<99;a++)
{
Driver_PWMSet(b,a);
delay_ms(5);
}
for(a=99;a>0;a--)
{
Driver_PWMSet(b,a);
delay_ms(5);
}
}
}
}
The difference between TIM2 and TIM1 is: TIM1->BKR |= TIM1_BKR_MOE;
TIM2 does not need to configure this register.
The output enable of OCi is controlled by the combination of CCiE, MOE, OISi, OSSR and OSSI bits (in TIM1_CCERi and TIM1_BKR registers).
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