S3C2440 Development Board Bare Metal Program Series 07—NAND FLASH Memory

1 Overview

My TQ2440 development board is equipped with 2M NOR FLASH and 512M NAND FLASH.

The feature of NOR FLASH is on-chip execution (XIP, eXecute In Place). Applications can run directly in NOR FLASH without having to read the code into the system RAM (which can save the cost of SRAM). NOR has high transmission efficiency and is very cost-effective at a small capacity of 1 to 4MB, but its low write and erase speed greatly affects its performance.

The characteristics of NAND FLASH are high storage density and fast writing and erasing speed, but it cannot directly address and run programs, and a special controller is required on the interface. In addition, NAND FLASH is very prone to bad areas, so a verification algorithm is required.

Therefore, NOR FLASH generally stores boot code and system firmware, which is equivalent to BISO. NAND FLASH is used to store data, which is equivalent to a hard disk.

Please refer to this article: 

Detailed explanation of the differences between RAM, NAND Flash, and NOR Flash

 The following will expand on several aspects including hardware connection, NANDFLASH internal structure, read and write operations, controller register settings, programming examples, etc.

2. Hardware connection of NANDFLASH

The NAND FLASH model on my TQ2440 development board is K9F4G08U0B, and the last B stands for the 3rd Generation.

For more information about NAND FLASH naming rules, see: Nand Flash Naming Rules  

The hardware connection relationship is shown in the figure below.

The GPA interface is reused as follows:

After checking the "TQ2440_V2 core board schematic", GPA21 is not connected, as shown below:

S3C2440 provides OM[1:0], NCON, GPG13, GPG14, GPG15 to select NAND FLASH boot. Refer to the S3C2440 Chinese manual, we can see:

The connection relationship provided by the TQ2440 core board:

As can be seen from the figure above, the resistor NR5 is not soldered, that is, NCON and GND are open circuit, so: NCON = 1, GPG13 = 1, GPG14 = 1, GPG15 = 0. That is, for advanced NAND Flash, each page is 2K bytes, requires 5 address cycles, and 8-bit width.

3. NANDFLASH internal structure

As shown below:

From the above figure, we can see the structure of K9F4G08:

There are 4096 blocks in total, each block has 64 pages, so there are 4096x64 = 256K pages in total, and each page can effectively store 2K bytes of data, so the total effective storage capacity is 512M bytes.

Accessing a piece of data requires a total of 5 cycles:

The 1st and 2nd cycles access the columns (A0-A11), that is, access the page, 2^11=2K

The 3rd, 4th, and 5th cycles access rows (A12-A29), that is, blocks, 2^(29-11)=2^18=256K.

Specifically, the program code is as follows:

NF_Send_Addr(0x00); 

NF_Send_Addr(0x00); 

NF_Send_Addr((page_number) & 0xff); 

NF_Send_Addr((page_number >> 8) & 0xff); 

NF_Send_Addr((page_number >> 16) & 0x3); 

It is divided into 5 cycles. Because reading and writing are generally performed in units of pages, the first two lines are sent 0x00, and the next three lines send the page number three times to A12--A19.

4. Read and write operations

The access operations (read, write, erase) to NAND FLASH can be performed according to the following steps:

a. Send command: What kind of operation is it, read, write, erase?

b. Sending address: Which address to operate on

c. Send data.

5. Controller register settings

The registers that need to be set for simple read and write programming include:

GPACON: Set GPA17-GPA22 as NAND FLASH controller signal;

NFCONF: Mainly determines the values ​​of TACLS, TWRPH0, and TWRPH1;

NFCONT: used to turn on the NAND FLASH controller and set whether to enable software locking;

NFCMD: used for writing commands;

NFADDR: used to write the address to be accessed;

NFDATA: The data to be written is placed here;

NFSTAT: Used to detect whether NAND FLASH is in busy state.

The settings for GPACON are as follows (although not used in GPA21):

rGPACON &=~(0X3F << 17) ;

rGPACON |= (0X3F<< 17) ;

For NFCONF, you need to understand the corresponding relationship between various parameters. The S3C2440 manual shows the following figure:

The timing relationship of NAND FLASH datasheet:

From the above figure, we can see that TWRPH0 = tWP, TWRPH1 = tCLH (= tALH)

In the example, FCLK=200MHz, HCLK=100MHz, PCKL=50MHz, so:

tCLH = 5ns，Duration = 10ns *(TWRPH1+1)   ==> TWRPH1=0

tWP = 12ns, Duration = 10ns *(TWRPH0+1) = 12min ==> TWRPH0>=1

tCLS - tWP = TACLS= 0ns，==> TACLS>=0，取TACLS=1.

NFCONT control bit 0

NFCMMD

 NFADDR

NFDATA (only the lower 8 bits are used)

NFSTAT

 Define the following macros:

#define NF_Send_Cmd(cmd)   {rNFCMD  = (cmd); }

#define NF_Send_Addr(addr)  {rNFADDR = (addr); }

#define NF_Send_Data(data)  {rNFDATA8 = (data); }      

#define NF_Enable() {rNFCONT &= ~(1<<1); } //nand flash controller enable

#define NF_Disable()                 {rNFCONT |= (1<<1); }

#define NF_Enable_RB() {rNFSTAT |= (1<<2); } // Enable RnB monitoring mode;

#define NF_Check_Busy()                  {while(!(rNFSTAT&(1<<0)));} 

#define NF_Read_Byte()          (rNFDATA8)

6. Read device ID procedure

The command to read the device ID is 90H, and the product information code is read in the next 5 cycles:

As can be seen from the above figure, there is a tREA delay after sending the Address.

The procedure for reading ID is as follows:

void NF_ReadID(unsigned char *buf)

{

int i;

NF_Enable();    

NF_Enable_RB();

NF_Send_Cmd(CMD_READID); // read id command

NF_Send_Addr(0x0);

for ( i = 0; i < 100; i++ );

        *buf = NF_Read_Byte();

*(buf+1) = NF_Read_Byte();

*(buf+2)    = NF_Read_Byte();

*(buf+3) = NF_Read_Byte();

*(buf+4) = NF_Read_Byte();

NF_Disable();

}

The main program is as follows:

#define ESC_KEY 0x1b

unsigned char table[]={0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,

0x38,0x39,0x41,0x42,0x43,0x44,0x45,0x46};

int Main()

{

int i;

unsigned char key ;

unsigned char nandID[5];

Uart0_Init(115200);

NF_Heat();

NF_ReadID(nandID);

Uart0_Printf( "nNand Flash ID:n" );

for(i=0;i<5;i++){

Uart0_Putc(table[nandID[i]>>4]);

Uart0_Putc(table[nandID[i]&0x0f]);

Uart0_Printf(" t");

}

Uart0_Printf( "nPress 'ESC' key to Exi n" );

while(1)

{

key = Uart0_Getc();

if( key == ESC_KEY ) { return 1; }

}

return 0;

}

7. Write/read a Block

First write 00-FF to the 17th Block, then read the data in the 17th Block and output it from serial port 0.

The main program is as follows: 

#define ESC_KEY 0x1b

unsigned char table[]={0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,

0x38,0x39,0x41,0x42,0x43,0x44,0x45,0x46};

int Main()

{

unsigned char key ;

unsigned char srcbuf[2048],dstbuf[2048] ;

unsigned int i=1 ;

Uart0_Init(115200);

NF_Heat();

for(i = 0 ; i < 2048 ; i++)

{

srcbuf[i] = i ;

}

NF_EraseBlock(17) ;

Uart0_Printf( "nWrite 0-FF to block[17] of NandFlash n" );

NF_WritePage(17,4,srcbuf) ;

Uart0_Printf( "nRead block[17] of NandFlash :n" );

NF_ReadPage(17,4, dstbuf);

for(i = 0 ; i < 2048 ; i++)

{

Uart0_Putc(table[dstbuf[i]/16]) ;

Uart0_Putc(table[dstbuf[i]%16]) ;

Uart0_Putc(' ') ;

}

Uart0_Printf( "nPress 'ESC' key to Exi n" );

while(1)

{

key = Uart0_Getc();

if( key == ESC_KEY ){ return 1; }

}

return 0 ;

}