STM32 interrupt priority description (preemptive and responsive priority)

Note: To view the registers, please refer to the "ARM Cortex-M4 Authoritative Guide". Since I use library development, I will not delve into the registers. The summary information comes from Atom's "STM32F4 Library Development Guide", which is summarized here for easy search.

STM32F4 interrupt grouping: STM32F4 divides interrupts into 5 groups, group 0 to 4. The grouping is defined by bits 10 to 8 of the SCB->AIRCR register. See the figure below:

Through this table, we can clearly see the configuration relationship corresponding to groups 0~4. For example, if the group is set to 3, then for all 82 interrupts, the highest 3 bits of the upper 4 bits of the interrupt priority register of each interrupt are the preemption priority, and the lower 1 bit is the response priority. For each interrupt, you can set the preemption priority to 0~7 and the response priority to 1 or 0.

The preemption priority is higher than the response priority, and the smaller the value, the higher the priority.

A high preemptive priority can interrupt a low preemptive priority, hence the name preemption; when the preemptive priorities are the same, the higher the response priority, the higher the response priority will be if it occurs at the same time, but it cannot interrupt the low response priority. The response expresses the response speed.

Let me explain two points here: first, if the preemption priority and response priority of two interrupts are the same, the interrupt that occurs first will be executed first; second, the preemption priority with a higher priority can interrupt the ongoing interrupt with a lower preemption priority. For interrupts with the same preemption priority, the response priority with a higher priority cannot interrupt the interrupt with a lower response priority.

Let's explain with an example: Assume that the interrupt priority group is set to 2, and then set the preemption priority of interrupt 3 (RTC_WKUP interrupt) to 2 and the response priority to 1. The preemption priority of interrupt 6 (external interrupt 0) is 3 and the response priority is 0. The preemption priority of interrupt 7 (external interrupt 1) is 2 and the response priority is 0. Then the priority order of these three interrupts is: interrupt 7>interrupt 3>interrupt 6.