【STM32】The basic principles and registers of ADC-EEWORLD

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STM32F1xx official information:

"STM32 Chinese Reference Manual V10" - Chapter 11 Analog/Digital Conversion (ADC)

Basic Introduction to ADC

Basic Definition of ADC

The abbreviation of Analog-to-Digital Converter. It refers to an analog/digital converter or an analog/digital converter. It refers to a device that converts a continuous variable analog signal into a discrete digital signal.

A typical analog-to-digital converter converts an analog signal into a digital signal that represents a proportional voltage value.

Key Characteristics of ADCs

12-bit successive approximation analog-to-digital converter;

With up to 3 ADC controllers, they can be used individually or in dual mode to increase the sampling rate;

Supports up to 23 channels and can measure up to 21 external and 2 internal signal sources;

Support single and continuous conversion modes;

Interrupts are generated when a conversion is completed, an injected conversion is completed, and an analog watchdog event occurs;

Automatic scanning mode from channel 0 to channel n;

Automatic calibration;

The sampling interval can be programmed per channel;

Both regular and injection channels have external trigger options;

The conversion result can be stored in a 16-bit data register in left-aligned or right-aligned mode.

ADC conversion time: maximum conversion rate 1us (maximum conversion speed is 1MHz, obtained when ADCCLK=14M and sampling period is 1.5 ADC clocks);

ADC power supply requirements: 2.4V-3.6V;

ADC input range: VREF- ≤ VIN ≤ VREF+.

STM32F10x series chip ADC channel and pin correspondence

As can be seen from the above figure, the STM32F103ZET6 has 3 ADC controllers, supporting a total of 23 channels, including 21 external and 2 internal signal sources; but each ADC controller can have a maximum of 18 channels, including 16 external and 2 internal signal sources.

Basic principles of ADC

ADC working block diagram

The block diagram of the ADC module looks complicated, so we will analyze it bit by bit.

ADC Pins

The leftmost column in the block diagram is the various pins of the ADC. Their names, signal types and functions are shown in the figure below:

Generally, VDD is 3.3V and VSS is grounded. Correspondingly, VDDA is 3.3V and VSSA is also grounded. The analog input signal should not exceed VDD (3.3V).

ADC Clock Configuration

The ADCCLK from the ADC prescaler marked in the block diagram is the clock source of the ADC module. Usually, the ADCCLK clock provided by the clock controller is synchronized with PCLK2 (APB2 clock). The RCC controller provides a dedicated programmable prescaler for the ADC clock.

One thing to note here is that, generally speaking: do not let the ADC clock exceed 14MHz, otherwise it may be inaccurate.

That is to say, if PCLK2 is set to 72MHz by default, it should be divided by 6 or 8.

ADC Interrupt

At the top of the block diagram, the various interrupts for the ADC are shown. It is obvious that the regular and injection group interrupts are generated when the conversion is completed, and when the analog watchdog status bit is set. They all have separate interrupt enable bits.

Note: The interrupts of ADC1 and ADC2 are mapped on the same interrupt vector, while the interrupt of ADC3 has its own interrupt vector.

There are three specific types of ADC interrupt events, as shown in the figure below:

ADC Channel Selection

As mentioned before, the ADC rule group conversion completion and injection group conversion completion can generate an interrupt, so what are the rule group and injection group? This is the middle part of the block diagram.

The STM32 ADC controller has many channels, so the module can switch to different input channels and perform conversions through the internal analog multiplexer. STM32 has specially added a variety of group conversion modes, which can be set by the program to automatically sample and convert multiple analog channels one by one. They can be organized into two groups: regular channel group and injection channel group.

For example, conversion may be completed in the following order: channel 3, channel 8, channel 2, channel 2, channel 0, channel 2, channel 2, channel 15.

Regular channel group: up to 16 channels can be arranged. The regular channel and its conversion order are selected in the ADC_SQRx register, and the total number of regular group conversions should be written to L[3:0] of the ADC_SQR1 register;

Injection channel group: Up to 4 channels can be arranged. The injection group and its conversion order are selected in the ADC_JSQR register. The total number of conversions in the injection group should be written to L[1:0] of the ADC_JSQR register.

When executing the scan conversion of the regular channel group, if there is an exception, the conversion of the injected channel group can be enabled. In other words, the conversion of the injected channel can interrupt the conversion of the regular channel. The regular channel can continue to convert only after the injected channel is converted.

Of course, one thing to note is: if the ADC_SQRx or ADC_JSQR registers are changed during a conversion, the current conversion is cleared and a new start pulse will be sent to the ADC to convert the newly selected group.

Maybe you don't quite understand it from the literal meaning? We can understand it more intuitively through graphics:

A less appropriate metaphor is that the conversion of the regular channel group is like the normal execution of the program, while the conversion of the injection channel group is like an interrupt handler outside the normal execution of the program.

ADC conversion method

The channels of the STM32 ADC can be organized into regular channel groups or injection channel groups, but the conversion modes can also include single conversion, continuous conversion, and scan conversion modes.

One-shot conversion mode

In single conversion mode, the ADC performs only one conversion. This mode can be started by setting the ADON bit in the ADC_CR2 register (only applicable to regular channels) or by an external trigger (applicable to regular channels or injection channels), and the CONT bit is 0.

Continuous conversion mode

In continuous conversion mode, another conversion is started as soon as the previous ADC conversion is completed. This mode can be started by an external trigger or by setting the ADON bit in the ADC_CR2 register, when the CONT bit is 1.

Scan Mode

This mode is used to scan a group of analog channels.

The scan mode can be selected by setting the SCAN bit of the ADC_CR1 register. Once this bit is set, the ADC scans all channels selected by the ADC_SQRX register (for regular channels) or ADC_JSQR (for injected channels). A single conversion is performed on each channel of each group. At the end of each conversion, the next channel of the same group is automatically converted. If the CONT bit is set, the conversion does not stop on the last channel of the selected group, but continues again from the first channel of the selected group.

It should be noted that if the interrupt is used in the scan mode, the interrupt will be generated after the last channel is converted. For continuous conversion, an interrupt will be generated after each conversion.

If the DMA bit is set, the DMA controller transfers the conversion data of the regular group channels to SRAM after each EOC. The conversion data of the injected channels are always stored in the ADC_JDRx register.

Analog watchdog

In addition to the regular group conversion completion and injection group conversion completion, the ADC interrupt can also be generated by simulated watchdog events.

If the analog voltage converted by the ADC is lower than the low threshold or higher than the high threshold, the AWD analog watchdog status bit is set. The threshold is located in the least significant 12 bits of the ADC_HTR and ADC_LTR registers. The corresponding interrupt is enabled by setting the AWDIE bit in the ADC_CR1 register.

It is important to note that the threshold is independent of the data alignment mode selected by the ALIGN bit on the ADC_CR2 register. The comparison is done before alignment. That is, the comparison is done before the data is saved to the data register (data alignment is explained below)!

By configuring the ADC_CR1 register, the analog watchdog can act on one or more channels:

External trigger conversion

Below the block diagram, it is shown that regular conversion and injection conversion can be triggered by external events (such as timer capture, EXTI line). If the EXTTRIG control bit is set, the external event can trigger the conversion. The EXTSEL[2:0] and JEXTSEL[2:0] control bits allow the application to select one of 8 possible events that can trigger the sampling of regular and injection groups.

Note: When an external trigger signal is selected as ADC regular or injected conversion, only its rising edge can start the conversion.

Automatic calibration

The ADC has a built-in self-calibration mode. Calibration can significantly reduce the accuracy errors caused by variations in the internal capacitor bank. During calibration, an error correction code (digital value) is calculated on each capacitor and this code is used to eliminate the errors introduced on each capacitor in subsequent conversions.

Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is complete, the CAL bit is reset by hardware and normal conversion can begin. It is recommended to perform an ADC calibration at power-up. After the calibration phase is complete, the calibration code is stored in ADC_DR.

Note: It is recommended to perform a calibration after each power-on. Before starting the calibration, the ADC must be in the power-off state (ADON=0) for at least two ADC clock cycles.

Data alignment

Since the ADC of STM32 is a 12-bit successive approximation analog-to-digital converter, and the data is stored in a 16-bit register, the ALIGN bit in the ADC_CR2 register selects the alignment of the converted data storage. The data can be left-aligned or right-aligned, as shown in the following figure:

The data value injected into the group channel conversion has the offset defined in the ADC_JOFRx register subtracted, so the result can be a negative value. The SEXT bit is the extended sign value.

For regular group channels, no offset value needs to be subtracted, so only 12 bits are valid.

Channel sampling time

The ADC uses several ADC_CLK cycles to sample the input voltage. The number of sampling cycles can be changed by the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be sampled at a different time.

The total conversion time is calculated as follows:

TCONV = sampling time + 12.5 cycles

For example: when ADCCLK = 14MHz and the sampling time is 1.5 cycles, TCONV = 1.5 + 12.5 = 14 cycles = 1μs.

Therefore, the minimum sampling time of ADC is 1us (ADC clock = 14MHz, sampling period is 1.5 cycles).

ADC related configuration registers

ADC Control Register 1 (ADC_CR1)

Function: Set scan mode, interrupt enable (conversion end, injection conversion end, simulated watchdog), dual mode selection (generally independent mode is selected), etc.

Note: In scan mode, the channel selected by the ADC_SQRx or ADC_JSQRx register is converted. If EOCIE or JEOCIE is set, the EOC or JEOC interrupt will be generated after the last channel is converted.

ADC Control Register 2 (ADC_CR2)

Function: Set data alignment, continuous conversion bit, ADC start bit, external trigger conversion (generally use software conversion SWSTART, JSWSTART).

ADC Sampling Time Register x (ADC_SMPRx)