Summary of STM32F4 peripheral clock configuration

See the end of the clock tree (stm32F407VGET6)

1. The first thing that needs to be clarified is the clock configuration   

The main clock and peripheral corresponding clock reference clock tree are as follows:

For example:

You can configure it as follows: That is, the default configuration in [1] (SetSysClock function of system_stm32F4xx.c)  

Configure SYSCLK, HCLK, PCLK2, PCLK1    

Configure the master clock:

Reference [1] has a good description:

The internal/external clock selection:

Configure RCC->CFGR through the corresponding register,

The internal clock HSI is selected at first, and then the external clock 8MHz crystal oscillator is used; if the external crystal oscillator is unstable, the internal clock is automatically used.

Another configuration (you can redefine the clock again in the main function when setting the RCC function) RCC function configuration:

The result

  System clock = 168M

  AHB=168M

  APB1=84M (divided by two PCLK1)

 APB2=168M (1-divided frequency PCLK2)

What are the allocations of each bus, and what is mounted on the AHB bus? What is mounted on the APB1 bus? What is mounted on the APB2 bus?

The bus matrix can be used to manage access arbitration between master buses, and the arbitration adopts a round-robin scheduling algorithm

For the specific buses to which the peripherals are connected, see p52, as shown in the following table

Among them: With the help of two AHB/APB bus bridges APB1 and APB2, full

Synchronous connection, allowing flexible selection of peripheral frequencies.

Table 1:

Clock Tree:

【1】STM32F4 Development Guide - Library Function Version

 【2】STM32F4XX Chinese Reference Manual