stm32 microcontroller clock understanding

Systick is slow, usually with a 32k external crystal, used for timing. Sysclk is the main clock, which is the highest 72M for the core and most peripherals. HCLK is the high-speed peripheral clock, which is for external devices, such as memory, flash

SYSCLK system clock, maximum 72MHz

HCLK: AHB bus clock, obtained by dividing the system clock SYSCLK. Generally, it is not divided, which is equal to the system clock passing through the bus bridge AHB--APB. By setting the division, the PCLK1 and PCLK2 clocks can be obtained from HCLK. However, the maximum of PCLK2 clock can reach 72MHz, while the maximum of PCLK1 is 36MHz. PCLK2 corresponds to APB2 peripherals. PCLK1 corresponds to APB1 peripherals.

AHB (HCLK) clock = SYSCLK = 72MHz

APB2 (PCLK2) clock = AHB clock = 36MHz

APB1 (PCLK1) clock = AHB 1/2 clock = 72MHzADC clock = PCLK2 1/4 = 9MHzPLL clock = HSE*9 = 72MHz

The clock is the pulse of the STM32 microcontroller and the driving source of the microcontroller. The corresponding clock must be turned on when using any peripheral. The advantage of this is that if a peripheral is not used, its clock can be turned off, thereby reducing the power consumption of the system, achieving energy saving and low power consumption.

The clock of the STM32 microcontroller can be provided by the following three clock sources:

1. HSI: High-speed internal clock signal. The clock (8M frequency) in the STM32 microcontroller has poor accuracy.

2. HSE: High-speed external clock signal with high precision (1) HSE external crystal/ceramic resonator (crystal oscillator) (2) HSE user external clock

3. LSE: Low-speed external crystal 32.768kHz mainly provides an accurate clock source and is generally used as an RTC clock

The stm32 microcontroller divides or multiplies the clock signal (such as HSE) by PLL to obtain the system clock, which is then divided to generate the clock used by the peripherals.

Understand the clock of the stm32 microcontroller. Here is how to use it. I will give an example of using the HSE clock.

Setting the clock process:

1. Reset the RCC register to the default value RCC_DeInit

2. Turn on the external high-speed clock crystal HSE RCC_HSEConfig (RCC_HSE_ON);

3. Wait for the external high-speed clock crystal to work HSEStartUpStatus = RCC_WaitForHSEStartUp();

4. Set AHB clock RCC_HCLKConfig;

5. Set high-speed AHB clock RCC_PCLK2Config;

6. Set the low speed AHB clock RCC_PCLK1Config

7. Set PLL RCC_PLLConfig

8. Enable PLL RCC_PLLCmd(ENABLE);

9. Wait for PLL to work while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)

10. Set the system clock RCC_SYSCLKConfig

11. Determine whether PLL is the system clock while (RCC_GetSYSCLKSource() != 0x08)

12. Open the peripheral clock RCC_APB2PeriphClockCmd()/RCC_APB1PeriphClockCmd() to be used

In STM32, there are five clock sources: HSI, HSE, LSI, LSE, and PLL.

　　①. HSI is a high-speed internal clock, RC oscillator, with a frequency of 8MHz.

　　②. HSE is a high-speed external clock that can be connected to a quartz/ceramic resonator or an external clock source with a frequency range of 4MHz~16MHz.

　　③. LSI is a low-speed internal clock, RC oscillator, with a frequency of 40kHz.

　　④. LSE is a low-speed external clock connected to a quartz crystal with a frequency of 32.768kHz.

　　⑤、PLL is a phase-locked loop frequency multiplication output, and its clock input source can be selected as HSI/2, HSE or HSE/2. The frequency multiplication can be selected from 2 to 16 times, but

The maximum output frequency shall not exceed 72MHz.

　　The system clock SYSCLK is the clock source for most components in STM32. The system clock can be selected as PLL output, HSI or HSE. The maximum frequency of the system clock is 72MHz. It is divided by the AHB divider and sent to each module. The AHB divider can be divided by 1, 2, 4, 8, 16, 64, 128, 256, 512. The clock output by the AHB divider is sent to 5 major modules:

　　①. HCLK clock sent to AHB bus, core, memory and DMA.

　　②. The system timer clock is sent to Cortex after being divided by 8.

　　③. Send the idle running clock FCLK directly to Cortex.

　　④、Send to APB1 divider. APB1 divider can select 1, 2, 4, 8, 16 frequency division, one of its outputs is used by APB1 peripherals (PCLK1, maximum frequency 36MHz), and the other is sent to timer (Timer) 2, 3, 4 frequency multiplier. The frequency multiplier can select 1 or 2 frequency multiplication, and the clock output is used by timer 2, 3, 4.

　　⑤. Send to APB2 divider. APB2 divider can select 1, 2, 4, 8, 16 frequency division, one of its outputs is used by APB2 peripherals (PCLK2, maximum frequency 72MHz), and the other is sent to Timer 1 multiplier. The multiplier can select 1 or 2 times, and the clock output is used by Timer 1. In addition, APB2 divider has one output for ADC divider, which is sent to ADC module after frequency division. ADC divider can select 2, 4, 6, 8 frequency division.

　　Among the above clock outputs, many have enable control, such as AHB bus clock, core clock, various APB1 peripherals, APB2 peripherals, etc. When you need to use a module, remember to enable the corresponding clock first.