Cortex-M3 exception interrupt and vector table definition

1. Cortex-M3 exception types

Cortex-M3 supports 256 interrupts (or exceptions), including 16-4-1=11 system exceptions (numbered 1-15), and up to 240 external interrupts (numbered greater than 16) - IRQ for short. The specific number of these 240 interrupt sources used is determined by the chip manufacturer. The interrupt signals generated by the peripherals, except for SysTick, are all connected to the interrupt input signal line of the NVIC. Typically, the processor generally supports 16 to 32 interrupts, of course there are also more than that.

All events that can interrupt normal execution can be called exceptions or interrupts. The difference between exceptions and interrupts in CM3 is:

Interrupts: All 240 interrupts are "unexpected emergencies" for the CM3 core. That is, the request signal comes from outside the CM3 core, from various on-chip peripherals and external peripherals, and is "asynchronous" to the CM3.

Exceptions: Exceptions are generated by the activities of the CM3 core, that is, when executing instructions or accessing memory, which is "synchronous" to the CM3.

The following table lists all the exceptions and external interrupts that Cortex-M3 can support. There are a number of system exceptions for fault handling, which can be caused by a variety of error conditions. NVIC also provides some fault status registers to facilitate the fault service routine to find out the specific cause of the exception.

In the interrupt control and status register of NVIC, there is a VECTACTIVE bit field; in addition, there is a special function register IPSR. In both of them, the exception currently being serviced is recorded and its number is given.

If an exception occurs that cannot be responded to immediately, it is said to be "pending". However, a few fault exceptions are not allowed to be suspended. The reason why an exception is suspended may be that the system is currently executing a service routine for a higher priority exception, or the exception is disabled due to the setting of the relevant mask bit. For each exception source, when it is suspended, there will be a corresponding "pending status register" to save its exception request. When the exception can be responded to, its service routine is executed, which is completely different from the traditional ARM. In the past, the device that generated the interrupt held the request signal; CM3 uses the NVIC's suspension status register to solve this problem. Therefore, even if the device has released the request signal later, the previous interrupt request will not be missed.

2. Cortex-M3 vector table

When the CM3 core responds to an exception, the corresponding exception service routine (ESR) will be executed. In order to determine the entry address of the ESR, CM3 uses a "vector table lookup mechanism". A vector table is used here. The vector table is actually a WORD (32-bit integer) array. Each subscript corresponds to an exception, and the value of the subscript element is the entry address of the ESR. The position of the vector table in the address space can be set, and the address of the vector table is indicated by a relocation register in the NVIC. After reset, the value of this register is 0. Therefore, a vector table must be included at address 0 for initial exception allocation.

For example, if exception 11 (SVC) occurs, the NVIC will calculate the offset as 11x4=0x2C, and then take the entry address of the service routine from there and jump in. It should be noted that there is an alternative here: type 0 is not an entry address, but gives the initial value of MSP after reset.