Four operating modes of on-chip RAM

1. Memory mapping: When the CPU accesses the address in this range, the address fetch packet in the corresponding address will be returned (other modes will return undefined data); the CPU cannot access the program RAM through the DMC; the user can determine the different starting addresses

of the program RAM by selecting different mapping modes (map0/map1). 2. Cache enable: (1) Initially, program instruction fetches at any address are considered cache misses;

first, the required instruction fetch packet is read in through the EMIF, and the instruction fetch packet is stored in the cache while being sent to the CPU. During this process, the CPU is suspended. (2) Subsequent accesses to cached addresses will cause cache hits, and the instruction fetch packet in the cache will be immediately sent to the CPU (3) When the program switches from memory mapping mode to cache enable mode, the cache area will be automatically flushed, which is also the only way to flush the cache.

3. Cache freeze: Keep the current state of the cache. The only difference from cache enable is that when a cache miss occurs, the instruction packet read in from the EMIF will not be stored in the cache at the same time, ensuring that the cached program will not be overwritten.

4. Cache bypass: The cache maintains its current state, ensuring that instructions can only be fetched from external storage space.