STM32 independent watchdog principle

The independent watchdog of STM32 is driven by a dedicated internal 40Khz low-speed clock, that is, it is still effective even if the main clock fails. Here we need to note that the clock of the independent watchdog is not an accurate 40Khz, but a clock that varies between 30 and 60Khz. It is just that we estimate it to be 40Khz. The watchdog is not very demanding on time, and a little deviation in the clock is acceptable.

Several registers related to independent watchdog

Working principle of independent watchdog: Write 0XCCCC in the key value register (IWDG_KR) to enable the independent watchdog. At this time, the counter starts to count down from its reset value OXFFF. When the counter counts to the end 0X000, a reset signal (IWDG_RESET) is generated. Whenever 0XAAAA is written to the register IWDG_KR, the value in IWDG_RLR will be reloaded into the counter to avoid a watchdog reset.

Write protection of prescaler register (IWDG_PR) and reload register (IWDG_RLR): IWDG_PR and IWDG_RLR registers have write protection function. To modify the value of these two registers, first write 0X5555 to IWDG_KR. Writing to this register with a different value or reloading (writing 0XAAAA) will restart the write protection.

2. Independent watchdog startup process

In this way, as long as we set the above three registers accordingly, we can start the STM32 independent watchdog. The startup process is as follows:

2.1. 1. Inhale 0X5555 into IWDG_KR

Through this step we have cancelled the write protection of IWDG_PR and IWDG_RLR. The next step is to set their initial values.

Set the initial values ​​of IWDG_PR and IWDG_RLR.

Let's calculate the watchdog feeding time (watchdog overflow time) calculation formula

All=((4*2^prer)*rlr)/40

 Tout is the watchdog overflow time (in ms), prer is the watchdog clock pre-division value (IWDG_PR value), ranging from 0 to 7, and rlr is the watchdog reload value (IWDG_RLR). For example, if we set prer to 4 and rlr to 625, we can calculate Tout = 64 * 625 / 40 = 1000ms, so the watchdog overflow time is 1S. As long as 0XAAAA is sucked into IWDG_KR once within this second, the watchdog will not be reset (it is also possible to write multiple times) (since the watchdog clock is not accurate to 40Khz, do not feed the dog too late to avoid a watchdog reset).

2.2. 2. Write 0XAAAA to IWDG_KR

This sentence can load the initial count value in the reload register (IWDG_RLR) into the watchdog counter (you can also use this command to feed the watchdog).

2.3. 3. Write 0XCCCC to IWDG_KR

Through this sentence, we have started the watchdog of STM32. After enabling the watchdog, we must feed the dog at a certain interval in the program, otherwise it will cause the program to reset. Taking advantage of this, we use an LED to indicate whether it is reset and verify the independent watchdog.

The watchdog core in STM32 is inside the chip and does not require an external circuit. Here we use two IO ports in the external circuit, one for inputting the dog feeding signal and the other for indicating whether the program is reset. The WK_UP button is used to feed the dog and DS0 is used to indicate program restart.