Design of multiple functional modules of universal testing machine based on STM32 and STM8 processors

    Based on STM32 and STM8 processors, multiple functional modules of the universal testing machine were designed. In order to improve the acquisition accuracy and speed of small signals, a hybrid phase-locked amplifier was designed using multiple processors, and digital processing was used for further processing, which has a high cost performance. In the displacement signal acquisition. The low-cost design was achieved using STM8S. Experiments show that this system meets the requirements of the universal testing machine in terms of speed and accuracy, and has a high overall cost performance.

    Universal material testing machine is a testing machine equipped with a fully digital measurement and control system. It is mainly used for mechanical property tests such as tensile peeling of rubber, plastic, metal, cement and other materials. As a precision testing instrument, material testing machine plays an extremely important role in the development of material science, industrial product and engineering structure design, effective use of materials, process improvement, product weight reduction and volume reduction, product quality improvement and cost reduction, as well as product safety and reliability and service life. At present, there is a lot of room for improvement in the function, accuracy and cost of traditional universal material testing machines in China. This paper is based on the STM32 processor of STMicroelectronics as the core of the acquisition and control system. In the acquisition of small signals such as force sensors, a hybrid phase-locked amplifier solution is designed, and multiple processors are used to complete small signal acquisition. Using the encoder interface of the 8-bit single-chip microcomputer STM8S and the PCI dedicated interface chip, a high-precision, simple interface circuit and cost-effective universal material testing machine solution is designed.

    1 System overall design and working principle

    The overall structure of the test machine is shown in Figure 1. The whole system includes five parts: the main control chip STM32, the data acquisition part, the control part, the computer communication interface and the wireless handheld operator. Data acquisition includes measuring force, deformation, displacement and other quantities. The two quantities of force and deformation are millivolt signals. In order to achieve high-precision acquisition and ensure a certain speed, a hybrid phase-locked amplifier is used to complete it. After the displacement signal is photoelectrically isolated, it enters the STM8S microcontroller, and is collected using its own encoder interface mode, and then communicates with the STM32 through IIC. There are two modes for control. For the servo motor, a pulse signal of a certain frequency is generated by a timer, and for the hydraulic system, it is controlled by DA. The communication with the PC is connected to SIM32 through a dedicated PCI interface chip. For the handheld operator of the manual control experiment, it is connected wirelessly.

    2 High-precision small signal acquisition module

    An important indicator of the testing machine system is the accuracy and speed of small signal acquisition such as force sensors. Moreover, the speed and accuracy of the acquisition system directly affect the performance of the control system. The full scale of these sensors is about 10 mV. To achieve a resolution of one hundred thousandth, it is necessary to be able to measure a 100 nV signal. The rapid and accurate acquisition of such a small signal is the key to this system. How to extract weak useful signals from background noise is the key to small signal acquisition. Among the various technologies for weak signal detection, the most widely used is the phase-locked amplifier with relatively high detection accuracy.

    The phase-locked amplifier is a device that uses the principle of cross-correlation to perform correlation operations on the detection signal and the reference signal. The basic principle of the phase-locked amplifier is shown in Figure 2. The principle of the phase-locked amplifier is based on the fact that the probability that the noise is both in the same frequency and in the same phase as the signal is very low. The phase-locked amplifier includes several parts such as the signal channel, the reference channel, and the correlator. The signal channel amplifies and filters the input signal accompanied by noise to filter out the noise outside the signal passband; the reference signal provides a signal with the same frequency and a certain phase difference as the measured signal; the correlator includes a phase-sensitive detector (multiplier) and a low-pass filter (integrator). After the phase-sensitive detector, the difference frequency term and the sum frequency term of the input signal and the reference signal will appear. Then the sum frequency term is filtered out by the low-pass filter, and the difference frequency term is retained. Finally, the DC signal output is only proportional to the amplitude of the measured signal.

    2.1 Lock-in amplifier hardware structure

    According to the different structures of the phase-sensitive detector of the lock-in amplifier, it can be divided into analog lock-in amplifier and digital lock-in amplifier. The analog lock-in amplifier has disadvantages such as temperature drift, noise, and poor system upgrade capability, but its speed is relatively fast. In comparison, the digital lock-in amplifier has good anti-interference performance, stable parameters, and is easy to upgrade, but due to a large number of calculations, the speed is relatively slow. This system adopts a hybrid design method to implement the multiplication operation with large amount of calculations with analog devices, and then, after AD sampling, the data is digitally filtered. While ensuring performance, the speed is maximized. Its overall structure is shown in Figure 3.

This system adopts the design of orthogonal vector phase-locked amplifier, which can avoid phase adjustment     of reference signal during measurement and avoid the influence of phase shift adjustment error on measurement accuracy. The signal channel consists of preamplifier , filter, main amplifier, etc. The preamplifier adopts LTC6910, which must have the characteristics of low noise and high gain. The input noise density of LTC6910 is 8 nV/, with programmable gain control, up to 100 times amplification. The filter circuit adopts TI's universal active filter UAF42, which can be configured as low-pass, high-pass, and band-pass filters. It has the characteristics of high integration, high reliability and flexible design.

    The main amplifier uses PGA 204, which is a low-cost, multi-purpose programmable gain amplifier from TI. The four-level fixed gain is 1, 10, 100, and 1000. It can be adjusted according to the range of the measured signal. In addition, the internal circuit of PGA204 is calibrated by laser technology, which makes the chip have low offset voltage and temperature drift, as well as a high common-mode rejection ratio. The reference signal is generated by the controller STM32, and two reference signals with a phase difference of 90 degrees are generated at the same time. The pre-processed signal to be measured and the two orthogonal reference signals enter the phase-sensitive detector respectively. The phase-sensitive detector uses a balanced modem AD630. AD630 has a two-way op amp structure controlled by a comparator, a simple external circuit, and a wide dynamic range . After completing the phase-sensitive detection, it enters the high-precision AD converter. This system uses TI's ADS1271.

    ADS1271 is a high-bandwidth 24-bit AD converter that achieves a breakthrough combination of DC accuracy and AC performance. It has a conversion rate of 105 kSPS and a signal-to-noise ratio of up to 109 dB . Since this system needs to complete two AD acquisitions at the same time, two ADS1271s are selected for simultaneous acquisition. After obtaining the digital signal, the dedicated digital processing unit performs calculations to finally obtain the amplitude of the signal to be measured. Since the multiplication operation with large computational complexity has been completed by analog devices, the amount of calculation here will not be too large, and this system uses the cost-effective STM32 processor.

    2.2 Principle of Lock-in Amplifier and Implementation of Digital Multi-point Averaging Algorithm

    This system uses digital multi-point averaging to process digital signals based on phase-locked operation to reduce the noise caused by AD sampling and improve the accuracy of the acquisition system. In this system, the measured signal is: x(t)=S(t)+N(t)=Asin(ωt+φ)+N(t). The sine reference signal and the cosine reference signal are: r1(t)=Bsin(ωt), r2(t)=Bcos(ωt). The cross-correlation functions of the measured signal and the two reference signals are:

    The multiplication operation has been implemented in the phase-sensitive detection part, and only addition operation is performed in digital processing. Due to the noise introduced in the previous AD sampling and analog devices, the AD sampling value is processed first when calculating the integral. The digital multi-point averaging method is used in this system, which is a method using the principle of synchronous accumulation and an effective method to extract effective signals from noise. The principle is as follows: suppose the signal submerged in the noise is, and sample i (i=1, 2, ...n) points in each sampling cycle , and sample m cycles. In this system, according to the sampling rate of ADS1 271 of 105 kSPS, the final sampling speed of 500  Hz is to be achieved . The design samples 30 points per cycle, and the cumulative number of sampling is set to 7 times. The sampling frequency of the reference signal in the phase-locked amplifier is 3.5 kHz. This design is based on the compromise between speed and performance.

    For linear cumulative averaging, the value of the i-th sampling point in the k-th sampling is:

    In the specific implementation, the main controller STM32 completes 30 samplings in each signal cycle. Each sampling is accumulated at a fixed sampling time, and the value of each sampling is saved. After completing m sampling cycles, the data is further processed and replaced with extreme value average filtering, which further improves the filtering effect to a certain extent. After calculating the final integral data, the amplitude of the signal to be measured is calculated according to the formula. At the beginning of each signal, MCU0 must send a synchronization pulse to ensure that the accumulated sampling value will not be misplaced. Every time AD completes a sampling, it interrupts and notifies MCU1, which specializes in digital processing, to read the data, accumulate, and save all the sampling values. In order to improve the processing capability, after completing the mth sampling, the data is sent to MCU2 for the final calculation of the signal to be measured, and MCU1 continues to accumulate and store the samples.

    In the test, a force sensor was used for testing, with a sampling frequency of 500Hz and a full range of 30 kN. The effective force measurement range is 1%-100%, and the measurement accuracy is 0.5%. When not divided into different levels, the resolution can reach 1/200,000. The speed and accuracy can meet the design requirements of the testing machine.

    2.3 Encoder displacement measurement module

    Incremental photoelectric encoders are usually used for displacement sensors (including those installed on the crossbeam and from the motor) and large deformation sensors in the test machine. It is a speed and position sensor with small size, high precision, fast response speed and stable performance. It has been widely used in the measurement field. The incremental encoder gives two pulse signals A and B with a phase difference of 90 degrees through the code disk rotating with the shaft, and then determines the rotation direction according to the phase relationship, and then uses a counter to add and subtract these pulses to indicate the angular displacement.

    The resolution of the photoelectric encoder is related to the number of pulses output per revolution. The more pulses, the higher the resolution. The introduction of frequency multiplication technology to subdivide the signal output by the encoder will further improve the measurement accuracy. The conventional method of implementing frequency multiplication is to process it through a logic circuit or to use a single-chip microcomputer after a series of processing. Now, there are also many chips on the market that are dedicated to encoder signal processing and directly output digital signals, such as the QA744808 chip from Quaker Semiconductor. These methods are either costly or relatively complex to process. This system uses the encoder interface mode function of the STM8S single chip to realize a simple encoder signal reading. In recent years, the STM8 and SWM32 series of single-chip microcomputers have been launched, which have added special designs for motor control, improved motor processing capabilities, and added encoder interfaces to be used in motor control. The incremental encoder can be directly connected to the MCU without the need for an external interface circuit.

    From the A and B signals, we can see that in one pulse cycle, the two signals change four times in total. If we can count both the rising and falling edges of the two signals, we can count the encoder four times in one cycle, thus achieving the purpose of quadruple frequency. As shown in Figure 5, in STM8S, by selecting the double-edge counting mode, the quadruple frequency function can be easily achieved. At the same time, when input jitter occurs, it will not cause the counter to add or subtract changes, which can effectively suppress interference.

    The encoder interface mode of STM8S exists in TIM1. In the hardware connection, the encoder differential signal is optically isolated by a high-speed optocoupler, and after level conversion, it is input into the TIM1_CB1 and TIM1_CH2 pins of TIM1. By configuring the TIM1_SMCR register, the counter counts at the edges of TI1 and TI2 at the same time. According to the jump sequence of the two input signals, counting pulses and direction signals are generated. When the counter overflows, the value is accumulated according to the direction, and a large range can be achieved. At the same time, it can be connected to STM32 through a pin of STM8S, and the encoder count can be cleared through the interrupt signal.

    In this system, a 3-way encoder signal acquisition circuit is designed. It is connected to STM32 through the IIC bus. The 20-pin STM8S103 is used here, which is very low in cost and simple in structure, and is a good choice.

    3 Conclusion

    In the design of the universal material testing machine system, the functions of several basic modules are realized, and a cost-effective solution is completed. The core of the acquisition system is realized by using a hybrid lock-in amplifier, and digital processing is used to ensure speed and accuracy. In addition, the solution does not require high performance of the processor, so the low-cost application of the lock-in amplifier is realized by using the STM32 processor.