The operation sequence of the program memory based on AT89S51

1. Control signals for 　　accessing program memory
　　
When the 　　AT89S51 microcontroller accesses the external program memory, the following three control signals are used.
　　
　　(1) ALE - used for low 8-bit address latch control.
　　
　　(2) PSEN (the inverse) - the "read enable" control signal for the external program memory. It is connected to the OE (the inverse) pin of the external EPROM.
　　
　　(3) EA (the inverse) - the control signal for accessing the internal and external program memory. When EA (the inverse) = 1, when the address sent by the microcontroller is less than the maximum address of the internal program memory, the internal program memory is accessed; when EA (the inverse) = 0, only the external program memory is accessed.
　　
　　If the instruction is read from the external EPROM, in addition to ALE for the low 8-bit address latch signal, the control signal also includes PSEN (the inverse), which is connected to the OE (the inverse) pin of the external EPROM. In addition, the PO port and the P2 port are also used. The PO port is used as the low 8-bit address bus and data bus in time sharing, and the P2 port is used as the high 8-bit address line.
　　
　　2. Operation timing
　　
　　The operation timing of the AT89S51 microcontroller on the external ROM is divided into two types, namely, the timing of executing non-MOVX instructions and the timing of executing MOVX instructions, as shown in the figure below.
　　
　　(1) There is no external RAM in the application system When there is no external RAM (or I/O) in the hardware system, there is no need to execute the MOVX instruction. When executing non-MOVX instructions, the operation timing is shown in the figure below (a). The PO port is used as a bidirectional bus for address/data multiplexing, which is used to input instructions or output the low 8-bit address PCL of the program memory. The P2 port is specifically used to output the high 8-bit address PCH of the program memory. The P2 port has an output latch function. Since the PO port is time-division multiplexed, the low 8-bit address PCL output by the PO port must first be latched in the latch using ALE, and then the PO port is used as a data port. In each machine cycle , the address latch is allowed to be valid twice. When ALE is at the falling edge, the low 8-bit address PCL on the PO port is latched in the latch. At the same time, PSEN (the inverse) is also valid twice in each machine cycle, used to select the off-chip program memory and read the instruction into the chip.
　　
　　When the system has no off-chip RAM (or I/O), this ALE valid signal appears on the pin at 1/6 of the oscillator frequency
　　
, which can be used as an external clock or timing pulse signal. 　　(2) When the application system is connected to an off-chip RAM, when executing the MOVX instruction to access the off-chip RAM (or I/O), the operation timing of the program memory changes. The main reason is that when executing the MOVX instruction, the 16-bit address should point to the data memory instead. The operation timing is shown in the following figure (b). Before the instruction is input, the addresses PCH and PCL output by the P2 port point to the program memory; after the instruction is input and determined to be a MOVX instruction, ALE latches the low 8-bit address of the off-chip RAM (or I/O) issued by the PO port in the S5 state of this machine cycle. If the instruction "MOVX A, @DPTR" or "MOVX @DPTR, A" is executed, the address is DPL (low 8 bits of data pointer); at the same time, DPH (high 8 bits of data pointer) appears on port P2. If the instruction "MOVX A, @R/" or "MOVX @R/, A" is executed, the content of R/ is the low 8 bits of address, and the content of the latch of port P2 will be on the line of port P2. The PSEN valid instruction fetch signal will no longer appear in the same machine cycle, and the ALE valid latch signal will no longer appear in the next machine cycle; and when RD/WR is valid, port PO will read/write the data in the data memory.
　　
　　It can be seen from the above figure (b):
　　
　　(1) When ALE is used as a timing pulse output, one ALE pulse will be lost when a MOVX instruction is executed.
　　
　　(2) Only in the second machine cycle when the MOVX instruction is executed, the data memory (or I/O) is read/written, and the address bus is used by the data memory.