MSP430F5438 Study Notes UART ACLK 9600-8-N-1-EEWORLD

Collect

1. Before initializing UART0, you need to initialize ACLK, SMCLK and MCLK. In the sample code, XT1 is used, ACLK is 32768, and SMCLK and MCLK are about 8MHZ.

2. The UART clock can refer to ACLK or SMCLK. In this example, ACLK is used. Since the ACLK clock is used, the serial port rate cannot exceed 32768. 9600 is a more appropriate choice.

3. There are two modes for generating baud rate of MSP430, low-frequency baud rate generation and oversampling baud rate generation. Low-frequency baud rate generation is used in the code.

4. The beginning of the code calls stdio, and the putchar function is rewritten in the function macro to direct the single-byte output to UART.

5. After the code is initialized, it outputs Hello MSP430, and then directly reflects the data received by the serial port. For example, if 123456 is sent, 123456 will be returned.

// Clock defaults
// FLL clock FLL select XT1
// Auxiliary clock ACLK selects XT1 32768Hz
// Main system clock MCLK selection DCOCLKDIV 8000000Hz
// Subsystem clock SMCLK selection DCOCLKDIV 8000000Hz
//UART clock selection ACLK
// Low frequency baud rate generation 9600-8-N-1
#include
#include
void clock_config(void);
void select_xt1(void);
void dco_config(void);
void uart_config(void);
int main(void)
{
clock_config(); // Initialize the clock
uart_config();
_UNITE();
P4DIR |= BIT0; //P4.0 output
printf("Hello MSP430!\r\n");
while(1)
{
P4OUT ^= BIT0;
__delay_cycles(1000000);
}
}
void clock_config(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog
select_xt1(); // Select XT1
dco_config(); // ACLK = XT1 = 32.768K
// MCLK = SMCLK = 8000K
}
void select_xt1(void)
{
// Start XT1
P7SEL |= 0x03; // P7.0 P7.1 peripheral function
UCSCTL6 &= ~(XT1OFF); // XT1 is turned on
UCSCTL6 |= XCAP_3; // Internal capacitor
do
{
UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 error flag
}while (UCSCTL7&XT1LFOFFG); // Check XT1 error flag
}
void dco_config(void)
{
__bis_SR_register(SCG0); // Disable FLL function
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // DCO maximum frequency is 16MHz
UCSCTL2 = FLLD_1 + 243; // Set DCO frequency to 8MHz
// MCLK = SMCLK= Fdcoclkdiv = (N+1)X(Ffllrefclk/n)
// N is the only value that needs to be calculated
// Ffllrefclk FLL reference clock, default is XT1
// n takes the default value, which is 1
// (243 + 1) * 32768 = 8MHz
__bic_SR_register(SCG0); // Enable FLL function
// Necessary delay
__delay_cycles(250000);
// Clear the error flag
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear all oscillator error flags
SFRIFG1 &= ~OFIFG; // Clear oscillator error
}while (SFRIFG1&OFIFG); // Wait for clear completion
}
void uart_config(void)
{
P3SEL = 0x30; // Select the multiplexing function of P3.4 and P3.5
UCA0CTL1 |= UCSWRST; // Software reset
UCA0CTL1 |= UCSSEL_1; // Select ACLK clock
UCA0BR0 = 3; // Get from table
UCA0BR1 = 0; // UCA0BRX and UCA0MCTL values
UCA0MCTL |= UCBRS_3 + UCBRF_0; //
UCA0CTL1 &= ~UCSWRST; //
UCA0IE |= UCRXIE; // Enable receive interrupt
}
int putchar(int ch)
{
UCA0TXBUF = ch;
while(!(UCA0IFG & UCTXIFG));
return ch;
}
#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break;
case 2: //Receive interrupt
while (!(UCA0IFG&UCTXIFG)); // Wait for sending to complete
UCA0TXBUF = UCA0RXBUF; // Receive buffer
break;
case 4:break; // Send interrupt
default: break;
}
}

Keywords：MSP430F5438 UART ACLK Reference address：MSP430F5438 Study Notes UART ACLK 9600-8-N-1

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