S3C2440 clock calculation-EEWORLD

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I have been studying S3C2440 for some time. I would like to explain the source of its system clock. If there are any errors, please correct me. I will be very grateful.

Mpll = (2*m * Fin) / (p * 2s)

m = M (the value for divider M) + 8, p = P (the value for divider P) + 2

The clock FCLK is the clock that the ARM core CPU runs. FCLK = (2*m * Fin) / (p * 2s). This clock is determined by the PLLCON control register.

Fin: external connection clock (the S3C2440 development board is connected to 12MHZ)

m: M (the value for divider M)+ 8

P: P (the value for divider P) + 2

m = (MDIV + 8), p = (PDIV + 2), s = SDIV

HCLK and PCLK are determined by FCLK, and the ratio of FCLK, HCLK, and PCLK is controlled by setting CLKDIVN.

Keywords：S3C2440 Reference address：S3C2440 clock calculation

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