S3C2440 Hardware Part 9: LCD-EEWORLD

Collect

background knowledge

1. Hardware requirements for LCD operation:

To make an LCD display text or image normally, it needs not only LCD driver but also corresponding LCD controller. Usually, the manufacturer will make LCD driver together with LCD glass substrate in the form of COF/COG, while LCD controller is realized by external circuit. Now many MCUs have integrated LCD controller, such as S3C2410/2440. LCD controller can generate control signal required by LCD driver to control STN/TFT screen.

2. S3C2440 internal LCD controller structure diagram:

Let's describe the LCD controller integrated in the S3C2440 according to the data sheet:

a: LCD controller consists of REGBANK, LCDCDMA, TIMEGEN, and VIDPRCS registers;

b: REGBANK consists of 17 programmable registers and a 256*16 palette memory, which are used to configure the LCD controller;

c: LCDCDMA is a dedicated DMA that can automatically transfer video data in the memory to the LCD driver. By using this DMA channel, the video data is displayed on the LCD screen without the intervention of the CPU;

d: VIDPRCS receives data from LCDCDMA, converts the data into a suitable data format, such as 4/8-bit single-scan, 4-bit double-scan display mode, and then transmits the video data to the LCD driver through the data port VD[23:0];

e: TIMEGEN is composed of programmable logic. It generates the control signals required by the LCD driver, such as VSYNC, HSYNC, VCLK and LEND, etc. These control signals are closely related to the configuration of LCDCON1/2/3/4/5 in the REGBANK register group. Through different configurations, TIMEGEN can generate different forms of these signals to support different LCD drivers (that is, different STN/TFT screens).

3. Common TFT screen working timing analysis:

External interface signals provided by LCD:

VSYNC/VFRAME/STV: vertical synchronization signal (TFT)/frame synchronization signal (STN)/SEC TFT signal;
HSYNC/VLINE/CPV: horizontal synchronization signal (TFT)/line synchronization pulse signal (STN)/SEC TFT signal;
VCLK/LCD_HCLK: pixel clock signal (TFT/STN)/SEC TFT signal;
VD[23:0]: LCD pixel data output port (TFT/STN/SEC TFT);
VDEN/VM/TP: data enable signal (TFT)/LCD drive AC bias signal (STN)/SEC TFT signal;
LEND/STH: line end signal (TFT)/SEC TFT signal;
LCD_LPCOE: SEC TFT OE signal;
LCD_LPCREV: SEC TFT REV signal;
LCD_LPCREVB: SEC TFT REVB signal.

All monitors display images from top to bottom and from left to right. What does this mean? Well, an image can be considered a rectangle, consisting of many neatly arranged dots in rows, and these dots are called pixels. So the display principle of this image on an LCD is:

A: The display pointer starts from the first point of the first row in the upper left corner of the rectangle, and is displayed on the LCD one by one. The timeline in the above timing diagram is VCLK, which we call the pixel clock signal;
B: When the display pointer is displayed to the right side of the rectangle, the line ends, and the action of this line is called 1 Line in the above timing diagram;
C: Then the display pointer returns to the left side of the rectangle and starts to display from the second line. Note that it takes a certain amount of time for the display pointer to return from the right side of the first line to the left side of the second line. We call it line switching;
D: And so on, the display pointer is displayed line by line to the lower right corner of the rectangle to complete the display of a picture. Therefore, the display of these lines on the timeline is HSYNC on the timing diagram;
E: However, the display of LCD is not a quick display of an image. In order to display it continuously and stably on the LCD, it is necessary to switch to another picture (the other picture can be the same or different from the previous picture, the purpose is just to display the image continuously on the LCD). Then these images are called frames, which are represented as 1 Frame on the timing diagram. Therefore, it can be seen from the timing diagram that 1 Line is just a line in 1 Frame;
F: Similarly, it takes a certain amount of time to switch between frames, which we call frame switching. Then the entire LCD display process can be represented as VSYNC on the timing diagram when viewed on the timeline.

The meanings of the clock delay parameters in the above timing diagram are as follows: (The LCD manufacturer will provide the corresponding data sheet for the values of these parameters)

VBPD (vertical back porch): indicates the number of invalid rows after the vertical synchronization signal at the beginning of a frame of image, corresponding to the upper_margin in the driver;
VFBD (vertical front porch): indicates the number of invalid rows before the vertical synchronization signal after the end of a frame of image, corresponding to the lower_margin in the driver;
VSPW (vertical sync pulse width): indicates the width of the vertical synchronization pulse, calculated by the number of rows, corresponding to the vsync_len in the driver;
HBPD (horizontal back porch): indicates the number of VCLKs from the start of the horizontal synchronization signal to the start of valid data of a row, corresponding to the left_margin in the driver;
HFPD (horizontal front porth): indicates the number of VCLKs from the end of valid data of a row to the start of the next horizontal synchronization signal, corresponding to the right_margin in the driver;
HSPW (horizontal sync pulse width): indicates the width of the horizontal synchronization signal, calculated by VCLK, corresponding to the hsync_len in the driver;

The values of the above parameters will be saved in the LCDCON1/2/3/4/5 registers in the REGBANK register group respectively: (For the operation of the registers, please refer to the LCD section of the S3c2440 data sheet)

LCDCON1: 17 - 8-bit CLKVAL
          6 - 5-bit scan mode (for STN screen: 4-bit single/dual scan, 8-bit single scan)
          4 - 1-bit color mode (1BPP, 8BPP, 16BPP, etc.)

LCDCON2: 31 - 24-bit VBPD
         23 - 14-bit LINEVAL
         13 - 6-bit VFPD
          5 - 0-bit VSPW

LCDCON3: 25 - 19-bit HBPD
         18 - 8-bit HOZVAL
          7 - 0-bit HFPD

LCDCON4: 7 - 0-bit HSPW

LCDCON5:

4. Frame Buffer:

Frame buffer is an interface provided by Linux for display devices. It describes some display devices as a buffer, allowing applications to access these graphics devices through the interface defined by FrameBuffer, without having to worry about the specific hardware details. For frame buffer devices, as long as the color value is written to the area corresponding to the display point in the display buffer, the corresponding color will be automatically displayed on the screen. Let's take a look at the correspondence between the buffer and the display point in different color bit modes:

5. LCD hardware circuit:

The above summary is transferred from: http://blog.chinaunix.net/u3/101649/showart.php?id=2188364

In conclusion:

1.s3c2440 provides us with a convenient LCD interface (GPC pins are used for VD[7:0], LCDVF[2:0], VM, VFRAME, VLINE, VCLK, LEND) (GPD pins are used for VD[23:8]) For details, see the datasheet of s3c2440.

2. For controlling TFT LCD, you only need to set registers LCDCON1~LCDCON5 (used to select LCD type, set time characteristics of various control signals, etc.) and LCDSADDR1~LCDSADDR3 (used to set frame memory address). For the settings of these registers:

         /*
         * Set the control registers LCDCON1~5 of the LCD controller
         * 1. LCDCON1:
         * Set the frequency of VCLK: VCLK(Hz) = HCLK/[(CLKVAL+1)x2]
         * Select LCD type: TFT LCD
         * Set display mode: 8BPP
         * Disable LCD signal output first

         * 2. LCDCON2/3/4:
         * Set the time parameters of the control signal
         * Set the resolution, that is, the number of rows and columns
         * Now, the frequency of the display can be calculated according to the formula:
         * When HCLK=100MHz,
         * Frame Rate = 1/[{(VSPW+1)+(VBPD+1)+(LIINEVAL+1)+(VFPD+1)}x
         * {(HSPW+1)+(HBPD+1)+(HFPD+1)+(HOZVAL+1)}x
         * {2x(CLKVAL+1)/(HCLK)}]
         * = 60Hz

         * 3. LCDCON5:
         * When the display mode is set to 8BPP, the data format in the palette is: 5:6:5
         * Set the polarity of the HSYNC and VSYNC pulses (this needs to refer to the specific LCD interface signal): Invert
         * Byte swap enable
         */

Among them, the parameters VBPD, VFPD, VSPW, HBPD, HFPD, and HSPW are provided by LCD manufacturers and can be modified according to their datashet.

===================================================================================

* Set the LCD controller address register LCDSADDR1~3

* The frame memory is completely consistent with the viewpoint,

* The image data format is as follows (at 8BPP, the data in the frame buffer is the index value in the palette):

* |----PAGEWIDTH----|

* y/x 0 1 2 639

* 0 idx idx idx ... idx

* 1 idx idx idx ... idx

* 1. LCDSADDR1:

* Set LCDBANK, LCDBASEU

* 2. LCDSADDR2:

* Set LCDBASEL: frame buffer end address A[21:1]

* 3. LCDSADDR3:

* OFFSIZE is equal to 0, PAGEWIDTH is equal to (640/2)

3. Partial code appreciation:

/*
* Initialize pins for LCD
*/

void Lcd_Port_Init(void)
{
    GPCUP = 0xffffffff; // Disable internal pull-up
    GPCCON = 0xaaaaaaaa; // GPIO pins for VD[7:0],LCDVF[2:0],VM,VFRAME,VLINE,VCLK,LEND
    GPDUP = 0xffffffff; // Disable internal pull-up
    GPDCON = 0xaaaaaaaa; // GPIO pins for VD[23:8]
    printf("Initializing GPIO ports..........\n");
}

/*
* Initialize LCD controller
* Input parameters:
* type: display mode
* MODE_TFT_8BIT_240320 : 240*320 8bpp TFT LCD
* MODE_TFT_16BIT_240320 : 240*320 16bpp TFT LCD
* MODE_TFT_8BIT_640480 : 640*480 8bpp TFT LCD
* MODE_TFT_16BIT_640480 : 640*480 16bpp TFT LCD
* MODE_TFT_8BIT_320240 : 640*480 16bpp TFT LCD
*/
void Tft_Lcd_Init(int type)
{
    switch(type)
    {
    ......
case omitted MODE_TFT_8BIT_320240:
        /*
         * Set the control registers LCDCON1~5 of the LCD controller
         * 1. LCDCON1:
         * Set the frequency of VCLK: VCLK(Hz) = HCLK/[(CLKVAL+1)x2]
         * Select LCD type: TFT LCD
         * Set display mode: 8BPP
         * Disable LCD signal output first

         * 2. LCDCON2/3/4:
         * Set the timing parameters of the control signal
         * Set the resolution, that is, the number of rows and columns
         * Now, the frequency of the display can be calculated according to the formula:
         * When HCLK=100MHz,
         * Frame Rate = 1/[{(VSPW+1)+(VBPD+1)+(LIINEVAL+1)+(VFPD+1)}x
         * {(HSPW+1)+(HBPD+1)+(HFPD+1)+(HOZVAL+1)}x
         * {2x(CLKVAL+1)/(HCLK)}]
         * = 60Hz

         * 3. LCDCON5:
         * When the display mode is set to 8BPP, the data format in the palette is: 5:6:5
         * Set the polarity of HSYNC and VSYNC pulses (this needs to refer to the interface signal of the specific LCD): Invert
         * Byte swap enable
         */

        LCDCON1 = (CLKVAL_TFT_320240<<8) | (LCDTYPE_TFT<<5) | \

                  (BPPMODE_8BPP<<1) | (ENVID_DISABLE<<0);

        LCDCON2 = (VBPD_320240<<24) | (LINEVAL_TFT_320240<<14) | \

                  (VFPD_320240<<6) | (VSPW_320240);

        LCDCON3 = (HBPD_320240<<19) | (HOZVAL_TFT_320240<<8) | (HFPD_320240);

        LCDCON4 = HSPW_320240;

        LCDCON5 = (FORMAT8BPP_565<<11) | (HSYNC_INV<<9) | (VSYNC_INV<<8) | \

                  (BSWP<<1);
        /*
         * Set the LCD controller's address registers LCDSADDR1~3
         * The frame memory is completely consistent with the view point,
         * The image data format is as follows (when 8BPP, the data in the frame buffer is the index value in the palette):
         * |----PAGEWIDTH----|
         * y/x 0 1 2 639
         * 0 idx idx idx ... idx
         * 1 idx idx idx ... idx

         * 1. LCDSADDR1:
         * Set LCDBANK, LCDBASEU

         * 2. LCDSADDR2:
         * Set LCDBASEL: the end address of the frame buffer A[21:1]

         * 3.LCDSADDR3:
         OFFSIZE is equal to 0, PAGEWIDTH is equal to (640/2)
         */

        LCDSADDR1 = ((LCDFRAMEBUFFER>>22)<<21) | LOWER21BITS(LCDFRAMEBUFFER>>1);

        LCDSADDR2 = LOWER21BITS((LCDFRAMEBUFFER+ \

                    (LINEVAL_TFT_320240+1)*(HOZVAL_TFT_320240+1)*1)>>1);

        LCDSADDR3 = (0<<11) | (LCD_XSIZE_TFT_320240/2);

        /* Disable temporary palette registers*/
        TPAL = 0;
        fb_base_addr = LCDFRAMEBUFFER;
        bpp = 8;
        xsize = 320;
        ysize = 240;
        break;
    default:
        break;

    }

}

/*
* Set the palette
*/

void Lcd_Palette8Bit_Init(void)
{
    int i;
    volatile unsigned int *palette;
    LCDCON5 |= (FORMAT8BPP_565<<11); // Set the data format in the palette to 5:6:5
    palette = (volatile unsigned int *)PALETTE;
    for (i = 0; i < 256; i++)
        *palette++ = DEMO256pal[i];
}
/*
* Change the palette to a color
* Input parameters:
* color: color value, format is 0xRRGGBB
*/
void ChangePalette(UINT32 color)
{
    int i;
    unsigned char red, green, blue;
    UINT32 *palette;
    palette=(UINT32 *)PALETTE;
    for (i = 0; i < 256; i++)
    {
        red = (color >> 19) & 0xff;
        green = (color >> 10) & 0xff;
        blue = (color >> 3) & 0xff;
        color = (red << 11) | (green << 5) | blue; // Format 5:6:5
        while ((LCDCON5>>16) == 2); // Wait until VSTATUS is not "valid"
        *palette++ = color;
    }
}
/*
* Set whether to output LCD power switch signal LCD_PWREN
* Input parameters:
* invpwren: 0 - Normal polarity when LCD_PWREN is valid
* 1 - Inverted polarity when LCD_PWREN is valid
* pwren: 0 - LCD_PWREN output is valid
* 1 - LCD_PWREN output is invalid
*/
void Lcd_PowerEnable(int invpwren, int pwren)
{
    GPGCON = (GPGCON & (~(3<<8))) | (3<<8); // GPG4 is used as LCD_PWREN
    GPGUP = (GPGUP & (~(1<<4))) | (1<<4); // Disable internal pull-up
    LCDCON5 = (LCDCON5 & (~(1<<5))) | (invpwren<<5); // Set LCD_PWREN polarity: normal/inverted
    LCDCON5 = (LCDCON5 & (~(1<<3))) | (pwren<<3); // Set whether to output LCD_PWREN
}
/*
* Set whether the LCD controller outputs a signal
* Input parameters:
* onoff:
* 0 : off
* 1 :Turn on
*/
void Lcd_EnvidOnOff(int onoff)
{
    if (onoff == 1)
        LCDCON1 |= 1; // ENVID ON
    else
        LCDCON1 &= 0x3fffe; // ENVID Off
}
/*
* Use temporary palette register to output monochrome image
* Input parameters:
* color: color value, format is 0xRRGGBB
*/
void ClearScrWithTmpPlt(UINT32 color)
{
    TPAL = (1<<24)|((color & 0xffffff)<<0);
}
/*
* Stop using temporary palette registers
*/
void DisableTmpPlt(void)
{
    TPAL = 0;
}

4. Upload the complete code, make to generate lcd.bin. Download it to nandflash and run it. Output in the serial terminal:

##### Test TFT LCD #####
[1] TFT320240 8Bit
[2] TFT240320 16Bit
[3] TFT640480 8Bit
[4] TFT640480 16Bit
Enter your selection: 1
Initializing GPIO ports..........
[TFT 64K COLOR(16bpp) LCD TEST]
1. Press any key to draw line
2. Press any key to draw circles
3. Press any key to fill the screem with one color
4. Press any key to fill the screem by temporary palette
5. Press any key to fill the screem by palette
6. Press any key stop the testing

You can see the LCD display.

Keywords：s3c2440 Hardware LCD Reference address：S3C2440 Hardware Part 9: LCD

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