AVR MCU fuse setting tips

       The configuration of AVR fuse bits is a relatively delicate task. Users often overlook its importance or find it difficult to master. The following are some key points and related matters that need to be noted when configuring AVR fuse bits. For the specific definition and function of ATmega128 fuse bits, please refer to the relevant chapters of this book. A complete summary table will be given in the appendix. 
(1) In the AVR device manual, the fuse bits are defined as programmed (Programmed) and unprogrammed (Unprogrammed). "Unprogrammed" means the fuse state is "1" (disabled); "Programmed" means the fuse state is "0" (allowed). Therefore, the process of configuring fuse bits is actually "configuring fuse bits to be unprogrammed state "1" or programmed state "0"".
(2) When using programming tool software that determines the fuse bit state value by selecting a check mark "√", please first read the software instructions carefully to understand whether "√" means setting the fuse bit state to "0" or "1".
(3) When using the programming download program in CVAVR, special attention should be paid. Since the initial state of most fuse bits is defined as "1" when the CVAVR programming download interface is initially opened, do not use the "all" option in its programming menu options. At this time, the "all" option will configure the fuse bits of the chip according to the initial state definition of the fuse bits, but in fact it is often not the configuration result required by the user. If you want to use the "all" option, you should first use "read->fuse bits" to read the actual state of the fuse bits in the chip, and then use the "all" option.
(4) Before using a new AVR chip, you should first check the configuration of its fuse bits, and then configure the fuse bits according to actual needs, and record the status of each fuse bit for filing.
(5) After the AVR chip is encrypted, only the data in the internal Flash and E2PROM of the chip cannot be read. The status of the fuse bits can still be read but the configuration cannot be modified. The chip erase command clears the data in the Flash and E2PROM, and at the same time configures the status of the two lock bits to "11", which is in an unlocked state. However, the chip erase command does not change the status of other fuse bits.
(6) The correct operating procedure is: when the chip is unlocked, download the running code and data, configure the relevant fuse bits, and finally configure the chip lock bit. After the chip is locked, if the fuse bit configuration is found to be incorrect, the chip erase command must be used to clear the data in the chip and unlock it. Then re-download the running code and data, modify the configuration-related fuse bits, and finally configure the chip lock bit again.
(7) When using ISP serial mode to download programming, the SPIEN fuse bit should be configured to "0". The SPIEN bit status is "0" by default when the chip leaves the factory, indicating that ISP serial mode data download is allowed. Only when this bit is in the programmed state "0" can ISP download be performed through the SPI port of the AVR. If this bit is configured to be unprogrammed "1", ISP serial mode data download is immediately prohibited. At this time, the SPIEN status can only be reset to "0" and ISP can be opened only through parallel mode or JTAG programming. Normally, the SPIEN state should be kept at "0". Allowing ISP programming will not affect the I/O function of its pins. As long as the hardware circuit design pays attention to the necessary isolation of the ISP interface and the devices connected in parallel, such as using series resistors or circuit breakers.
(8) When your system does not use the JTAG interface to download programming or real-time online simulation debugging, and the pins of the JTAG interface need to be used as I/O ports, the fuse bit JTAGEN must be set to "1". The JTAGEN state defaults to "0" when the chip leaves the factory, indicating that the JTAG interface is allowed and the external pins of JTAG cannot be used as I/O ports. When the JTAGEN state is set to "1", the JTAG interface is immediately disabled. At this time, JTAG can only be reset to "0" and JTAG can only be opened through parallel mode or ISP programming.
(9) In general, do not set the fuse to define the RESET pin as I/O (such as setting the ATmega8 fuse RSTDISBL to "0"). This will cause the ISP download programming to fail, because before entering the ISP mode programming, the RESET pin needs to be pulled low to put the chip into the reset state first.
(10) When using an AVR chip with an internal RC oscillator, pay special attention to the configuration of the fuse CKSEL. In general, the CKSEL bit of the chip defaults to using the internal 1MHz RC oscillator as the system clock source when it leaves the factory. If you use an external oscillator as the system clock source, do not forget to correctly configure the CKSEL fuse first, otherwise the timing of your entire system will have problems. When your design does not use an external oscillator (or a specific oscillator source) as the system clock source, do not misoperate or mistakenly configure the CKSEL fuse to use an external oscillator (or other different types of oscillator sources). Once this happens, the chip cannot be operated using the ISP programming method (because the ISP method requires the chip's system clock to work and generate timing control signals), and the chip looks "broken". At this time, the only way to save it is to remove the chip and use parallel programming, or use JTAG (if JTAG is allowed and the target board has a JTAG interface). Another way to save it is to try to temporarily superimpose different types of oscillation clock signals on the crystal pin of the chip. Once the ISP can operate the chip, immediately configure CKSEL to use the internal 1MHz RC oscillator as the system clock source, and then reconfigure CKSEL correctly according to the actual situation.
(11) When using an AVR chip that supports IAP, if you do not use the BOOTLOADER function, be careful not to set the fuse bit BOOTRST to "0", which will cause the chip to not start executing the program from 0x0000 of Flash when powered on. The default state of the BOOTRST bit is "1" when the chip leaves the factory. For the configuration of BOOTRST, the design of the BOOTLOADER program and the application of IAP, please refer to the relevant content of this chapter.
The role of the fuse bit during on-site debugging.
Question 1: System startup time. If the fuse bit is not configured, the system defaults to the internal clock, so the system startup time is relatively long. Configure the fuse to an external crystal oscillator. This is normal. The cause can be found in item 10 above.
Problem 2: The serial port does not operate normally. If the fuse is not configured, the default is a 1M crystal oscillator, so the calculation of the set baud rate will be incorrect. Garbled characters or different serial ports appear.