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Play with AT32F437 (4) --- Using SPI transmission as an example to explore the internal flash performance [Copy link]

 This post was last edited by RCSN on 2021-12-24 21:06

According to the Yatli propaganda, AT32F437 can reach up to 4M flash and 512K ram. The model of the host is AT32F437VMT7, which happens to have the highest storage capacity. So I want to test the read performance of such a large flash space, which is also the focus of this post.

As can be seen from the figure, the internal flash memory is divided into ZW and NZW, which are the so-called zero wait area and non-zero wait area. The zero wait area is 256K, which means that 256K of SRAM is used for FLASH flashing when used for transportation. Therefore, if the SRAM is allocated to the highest 512K, the zero wait area will be reduced and will not be allocated here.

So how to test the read performance of this flash memory? The author conducted two experiments, using SPI DMA transmission to transfer data from SRAM to SPI peripherals, and from flash memory FLASH to SPI peripherals. In other words, you can put an array of 320*240 pictures in SRAM and in flash memory FLASH, and then judge the read performance of the two by the transmission time.

I divided SPI to the maximum frequency, which is 2, so it is about 65M.

SRAM is transferred to SPI via DMA

As can be seen from the figure, a 320*240 resolution picture is transmitted in 18ms. According to the frame rate, (1000ms/18ms) = 55fps, which means a refresh rate of about 55fps. At the main frequency of 288M, the SPI performance is still acceptable.

Flash FLASH is transferred to SPI via DMA

Here, the author placed 26 images in the flash memory FLASH and one in the SRAM. As can be seen from the figure, the refresh time of 27 images is about 639Ms, and each image is about 24ms, which is 42fps. But please note that during my experiment, one image happened to be in the zero-wait area, and the refresh time of the two images differed by 7ms. Not only is the frame rate different by 17fps, but the performance gap of flash memory reading is still very large , especially when running instructions in the so-called non-zero wait area, which is very scary.

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You are so awesome, Zha Zha C. You are getting deeper and deeper.   Details Published on 2021-12-24 16:45
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1084534438 欢迎交流  [加油,一切皆有可能]

 
 

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This post was last edited by RCSN on 2021-12-24 21:06

It can be seen that the so-called zero-wait area is just moved from the flash to the SRAM when power is turned on. The read performance difference between the zero-wait area and the non-zero-wait area is more than 7ms.

From the perspective of flash read performance, the refresh rate is 17fps lower than that of SRAM. The difference is that 17 images are refreshed less in 1 second. The speed of executing instructions is still quite poor.

Although the nominal 4M flash memory has a large capacity, from the performance point of view, the only area that can really improve efficiency is the zero-wait area, that is, the 256K space. For some algorithms and controls, it is best to execute them in the so-called zero-wait area.

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You are so awesome, Zha Zha C. You are getting deeper and deeper.

This post is from Domestic Chip Exchange

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This is also called playing deep, uncle, you don't have this  Details Published on 2021-12-24 17:17
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默认摸鱼,再摸鱼。2022、9、28

 
 
 

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freebsder posted on 2021-12-24 16:45 Awesome, Zha Zha C, the more you play, the deeper you go.

This is also called playing deep, uncle, you don't have this

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