s3c2410 interrupt exception handling

There are two ways to store the exception vector table of ARM920T, one is low-end storage (starting from 0x00000000), and the other is high-end storage (starting from 0xfff000000). I will explain why there are two ways to store in the article introducing MMU. This article adopts the low-end mode. ARM920T can handle 8 exceptions, which are:
Reset, Undefined instruction, Software Interrupt, Abort (prefetch), Abort (data), Reserved, IRQ, FIQ.
The following is a system source code fragment using the low-end mode:

_start: b Handle_Reset b HandleUndef b HandleSWI b HandlePrefetchAbort b HandleDataAbort b HandleNotUsed b HandleIRQ b HandleFIQ ….. … .. other codes …

    The above snippet usually appears in an assembly file called "head.s". The statement "b Handle_Reset" is the first statement to be executed after the system is powered on. That is to say, the binary code of this part of the code must be located at the very beginning of the memory (this is the low-end storage mode), because after powering on, the CPU will fetch the first instruction from 0x00000000 of SDRAM and execute it.

Address Instruct 0x00000000: b Handle_Reset 0x00000004: b HandleUndef 0x00000008: b HandleSWI 0x0000000C: b HandlePrefetchAbort 0x00000010: b HandleDataAbort 0x00000014: b HandleNotUsed 0x000000 18: b HandleIRQ 0x0000001C: b HandleFIQ

    The above is the distribution of the program segment after it is loaded into the memory after the system is powered on. We can see that each instruction occupies 4 bytes.
    After power-on, the PC pointer will jump to Handle_Reset to start running. In the future, whenever an exception occurs in the system, the CPU will start looking up the table from 0x00000000 in the memory according to the exception number and do the corresponding processing. For example, if the system triggers an IRQ exception, and IRQ is the 6th exception, the CPU will point the PC to the address 0x00000018 (4*6=24=0x00000018) to run. The instruction at this address is to jump to the "interrupt exception service routine" (HandleIRQ) to run. The above is a brief introduction to the exception vector table. Now we can enter the topic of our article "interrupt exception handling". The interrupts of s3c2410 are divided into fast interrupts (FIQ) and ordinary interrupts (IRQ). The focus of our discussion is ordinary interrupts (IRQ).
The interrupt exception handling module of s3c2410 is composed of the following registers:
  SRCPND (SOURCE PENDING REGISTER)
  INTMOD (INTERRUPT MODE REGISTER)
  INTMSK (INTERRUPT MASK REGISTER)
  PRIORITY (PRIORITY REGISTER)
  INTPND (INTERRUPT PENDING REGISTER)
  INTOFFSET (INTERRUPT OFFSET REGISTER)
  SUBSRCPND (INTERRUPT SUB SOURCE PENDING)
  INTSUBMSK (INTERRUPT SUB MASK REGISTER)

Below I will explain the role of each register in an interrupt handling process:
    The two registers SRCPND/SUBSRCPND are functionally the same. They are interrupt source pin registers. In an interrupt exception handling process, the first register encountered after the interrupt signal enters the interrupt exception handling module is SRCPND/SUBSRCPND. The function of these two registers is to indicate which interrupt request is triggered. The valid bits of SRCPND are 32, and the valid bits of SUBSRCPND are 11. Each bit of them represents an interrupt source. SRCPND is the main interrupt source pin register, SUBSRCPND is the sub interrupt source pin register.
Here are the bits of SRCPND:

   The initial value of each bit is 0. Assuming that the system triggers the TIMER0 interrupt, the 10th bit will be set to 1, indicating that the TIMER0 interrupt is triggered and the interrupt request will be processed (if the interrupt is not masked). The situation of SUBSRCPND is the same as that of SRCPND, so I will not talk about it here. The
    effective bits of the INTMOD register are 32 bits, and each bit corresponds to each bit in SRCPND. Its function is to specify the interrupt source processing mode corresponding to the bit (IRQ or FIQ). If a bit is 0, the interrupt corresponding to the bit is processed in IRQ mode, and if it is 1, it is processed in FIQ mode. The initialization value of this register is 0x00000000, that is, all interrupts are processed in IRQ mode. (For details, please refer to the s3c2410 operation manual).
The INTMSK/INTSUBMSK register is an interrupt mask register, INTMSK is the main interrupt mask register, and INTSUBMSK is the secondary interrupt mask register. The effective bit of INTMSK is 32, and the effective bit of INTSUBMSK is 11. Each bit of these two registers corresponds to SRCPND and SUBSRCPND respectively. Their function is to determine whether the interrupt request corresponding to the bit is processed. If a bit is set to 1, the interrupt corresponding to the bit will be ignored after it is generated (the CPU does not process the interrupt request), and it will be processed if it is set to 0. The values ​​of these two registers after initialization are 0xFFFFFFFF and 0x7FF, that is, all interrupts are masked by default.
So far, we have explained
five registers, SRCPND, INTMOD, INTMSK, SUBSRCPND, and INTSUBMSK. Before continuing to explain the PRIORITY register, let's take a look at a picture.

   Let's make it clear first. What we are going to discuss now is the problem of determining the priority of interrupts. Why do interrupts have priority? We know that the CPU can only process one interrupt source at a time. If there are three interrupts at the same time, in what order should the CPU process these three interrupts? This is exactly why priority determination is introduced. Through priority determination, the CPU can process interrupt requests one by one in a certain order. The priority determination of 3sc2410 is divided into two levels.
    As shown in the figure above, the 32 interrupt sources corresponding to the SRCPND register are divided into 6 groups in total, and each group is managed by an ARBITER (0~5) register. The interrupt must first be determined by the ARBITER (0~5) of the group to which it belongs for the first priority determination (first level determination) before being sent to ARBITER6 for the final determination (second level determination). The priorities of the six groups ARBITER (0~5) are fixed and cannot be changed. That is to say, the interrupt group controlled by ARBITER0 has the highest priority (the interrupt generated by this group will always be passed to ARBITER6 as REQ0 after the first level judgment), followed by ARBITER1, ARBITER2, ARBITER4, ARBITER4, ARBITER5. What we can control is the priority order of each interrupt in a group. How to control? Control through the PRIORITY register:]
The following is the parameter table of each bit of the PRIORITY register

   From the table, we can know that the bits in the PRIORITY register are divided into two types, one is ARB_MODE, the other is ARB_SEL, ARB_MODE type has 5 groups corresponding to ARBITER (2~6) (PS: This should be corrected to ARB_MODE type has 7 groups corresponding to ARBITER (0~6), and there is a continuation table in the above table in the datasheet, which is ARB_MODE1-0), and ARB_SEL type has 7 groups corresponding to ARBITER (0~6). Now I will take ARBITER2 as an example to explain the relationship between the interrupt group and ARB_SEL and ARB_MODE in the PRIORITY register.
  First, we can see that the interrupt group managed by the ARBITER2 register includes 6 interrupts, namely INT_TIMER0, INT_TIMER1, INT_TIMER2, INT_TIMER3, INT_TIMER4, INT_UART2, and their default interrupt request numbers are REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5. Let's first look at ARB_SEL2 in the PRIORITY register. This parameter consists of two bits and its initial value is 00. From the table, we can see that 00 defines an order of 0-1-2-3-4-5, which is the priority order of this group of interrupt groups. This order indicates that INT_TIMER0 with interrupt request number 0 (REQ0) has the highest interrupt priority, followed by INT_TIMER1, INT_TIMER2, etc. Suppose now the value of ARB_SEL2 is set to 01. Then a new priority order will be used, and the priority order corresponding to 01 is 0-2-3-4-1-5. It can be seen that the highest and lowest priority interrupt requests have not changed from before, but the INT_TIMER1 interrupt, which was originally at the second priority, has now become the fifth priority. From the situation when ARB_SEL2 is set to 00, 01, 10, and 11, we can see that except for the highest and lowest priorities, the priorities of other interrupts are actually rotated. In order to achieve the goal of treating each interrupt equally, we can let the priority order automatically rotate after each interrupt request is processed. How to make it rotate automatically? We can achieve this goal through ARB_MODE2. This parameter has only 1 bit. Setting it to 1 means turning on the priority order rotation of the corresponding interrupt group, and 0 means turning it off. In fact, when this bit is 1, after each interrupt of a group is processed, the ARB_SEL of the group will increase by 1 (after reaching 11, it will be restored to 00).
    Now we set ARB_MODE2=1, ARB_SEL2=00, then the current priority order of ARBITER2 is 0-1-2-3-4-5. Assume that the interrupt request No. 1 INT_TIMER1 and the interrupt request No. 2 INT_TIMER2 of the group are triggered at the same time. After judging the priority, the CPU decides to send the INT_TIMER1 interrupt to ARBITER6 first (making the final priority judgment in ARBITER6), and then send the INT_TIMER2 interrupt to ARBITER6. Please note that after INT_TIMER1 is processed, the priority order of the middle section of the group is automatically rotated. After the rotation, the priority order of ARBITER2 becomes 0-2-3-4-1-5. Assuming that INT_TIMER1 and INT_TIMER2 of the group are triggered at the same time at some point in the future, the CPU will prioritize INT_TIMER2 at this time. If we set ARB_MODE2=0, the interrupt priority order of the reorganized group will not change under any circumstances unless we manually reset the value of ARB_SEL2.
    Phew... So tired... Finally finished talking about the troublesome priority-_-... continue...
The INTPND register may be a register that we need to pay special attention to in the entire interrupt processing process. Its operation is quite special. How is it special? Please listen to me slowly. :] Let 
's take a look at the detailed function list of each register first

    As you can see, the INTPND register looks exactly the same as the SRCPND register, but they play different roles in interrupt exception processing. If SRCPND is the first place that the interrupt signal passes through after entering the interrupt processing module, then INTPND is the last register that the interrupt signal passes through in the interrupt processing module. Each of its bits corresponds to an interrupt request. If the bit is set to 1, it means that the corresponding interrupt request is triggered. At this point in the description, you may find that it not only looks exactly the same as SRCPND, but also has the same functions. In fact, they have significant differences in function. SRCPND is the interrupt source pin register. A bit set to 1 indicates that the corresponding interrupt is triggered. However, we know that the system can trigger several interrupts at the same time. As long as the interrupt is triggered, the corresponding bit of SRCPND is set to 1, that is, SRCPND can have several bits set to 1 at the same time. However, INTPND is different. Only one bit can be set to 1 at a time. If a bit of INTPND is set to 1 (the interrupt corresponding to the bit has the highest priority among all the triggered interrupts and the interrupt is not masked), it means that the CPU is about to or has been processing the interrupt corresponding to the bit. So we can have a summary: SRCPND indicates what interrupt has been triggered, and INTPND indicates that the CPU is about to or has been processing a certain interrupt.
Special attention: Whenever an interrupt is processed, we must manually set the bit corresponding to the interrupt in the three registers SRCPND/SUBSRCPND and INTPND from 1 to 0. I just said that the operation of INTPND is very special. Its special feature is that when we want to set a bit with a value of 1 in the register to 0, we do not set the position to 0, but to 1. Assume SRCPND = 0x00000003, INTPND = 0x00000001, this value indicates that interrupt 0 and interrupt 1 are currently triggered, but interrupt 0 is currently being processed. After processing, we should set INTPND and SRCPND like this:
  SRCPND = "0x00000002" // Bit 0 is set to 0
  INTPND = 0x00000001 // Bit 0 is set to 0 (the method is to write 1 to this bit)
The function of the INTOFFSET register is very simple. It is only used to indicate which interrupt is being processed. The following is a detailed list of the functions of each bit of this register

    If INT_TIMER0 is triggered, the value of this register is 10, and so on.
    Now I will use a diagram to illustrate the entire interrupt process.

The above diagram clearly illustrates an interrupt exception handling process.
    Below I will use the three interrupts INT_TIMER0, INT_TIMER2 and INT_UART0 to fully introduce an interrupt exception handling. First, we have to make a few assumptions:

Assumption 1: The masking of these three interrupts is canceled.
Assumption 2: ARB_MODE2 and ARB_MODE5 in the PRIORITY register are both 0, and the priority is not automatically rotated. At any time,
      the priority order of the interrupt group controlled by ARBITER2 and ARBITER5 is 0-1-2-3-4-5 and 1-2-3-4 respectively.
Assumption 3: These three interrupts are all IRQ type.
Assumption 4: These three interrupts are triggered at the same time.
The three interrupts INT_TIMER0, INT_TIMER2 and INT_UART0 are triggered at the same time. At this time, the three interrupt signals flow to the SRCPND register, so that the 10th, 12th and 28th bits in the register are set to 1. The interrupt signal continues to flow forward through the INTMASK register. These three interrupts are not masked, so the signal further flows through the INTMODE register. These three interrupts are all IRQ types, so the interrupt signal continues to flow forward to the PRIORITY register. After priority judgment, the INT_TIMER0 interrupt signal sets the 10th bit of the INTPND register to 1 (INT_TIMER0 has the highest priority). At this time, the value of the INTOFFSET register is 10, and the CPU turns to the corresponding interrupt service routine for processing. After processing, our program sets the 10th bit of INTPND and SRCPND to 0, and the INT_TIMER0 interrupt is processed. At this time, the 12th and 28th bits of SRCPND are still 1 (these two interrupt requests have not been processed), so they will continue to be processed by the CPU in the way just described.
Let's talk about interrupt exception processing first:]

 

The above is the original post content. Thanks to the author again. . .

 

PS:

In the process of interrupt experiment on the bare board of 2410, from the perspective of a novice, I combined some things I learned with the previous theory of ARM architecture:

 

1. In the ARM processor, r13 (sp) and r14 (lr) correspond to 6 physical registers in different states, one of which is shared by user and system modes, and the others correspond to 5 exception modes. To use interrupts in subsequent programs, you should first set up the stacks of various modes to be used, such as setting the sp of IRQ and system mode:

2. If you use interrupt control such as buttons, which belongs to external interrupts (External Interrupt), you need to configure the EINT related registers.