//The clock source of the independent gatekeeper is the internal low-speed clock 128khz divided by 2, which is 64khz
Keywords：STM8S
Reference address：STM8S independent watchdog configuration and use
//Select IWDG_Prescaler_128
//64/128 = 0.5 khz 2ms period
#define IWDG_500MS_REST (uint8)250 #define IWDG_400MS_REST (uint8)200 #define IWDG_300MS_REST (uint8)150 #define IWDG_250MS_REST (uint8)125 #define IWDG_200MS_REST (uint8)100 #define IWDG_100MS_REST (uint8)50 #define IWDG_50MS_REST (uint8)25 #define IWDG_4MS_REST (uint8)2 IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable); //Agree to operate independent watchdog IWDG_SetPrescaler(IWDG_Prescaler_128); //Watchdog prescaler IWDG_SetReload(IWDG_200MS_REST); //Set the watchdog reset time IWDG_Enable(); //Start independent watchdog IWDG_ReloadCounter(); //Watchdog reset If you don't want watchdog reset to occur during normal use, run This instruction
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