void can_signal(void)
Keywords:STM32 CAN
Reference address:CAN error interrupt 1 in STM32
{
unsigned char data can_irq;
unsigned char data temp;
x_wdgtime();
can_irq = InterruptReg;
if(can_irq&ALI_Bit)
{ // Arbitration lost bit
++al_counter;
temp=ArbLostCapReg; // Read arbitration lost register
alc_current=temp&0x1F; // Get the current arbitration lost position
}
if(can_irq & BEI_Bit)
{ // Bus error interrupt
temp=ErrCodeCapReg;
buse_current=temp&0x3F;
temp=temp&0xD0; //Get the type of bus error
switch (temp)
{
case 0x00: ++bite_counter;
case 0x40: ++forme_counter;
case 0x80: ++stuffe_counter;
case 0xd0: ++othere_counter;
}
}
if(can_irq & EPI_Bit)
{ // Negative error interrupt,
// When the receive or send error count exceeds 127, the error state becomes a passive error
if((RxErrCountReg>127)||(TxErrCountReg>127)) errstatus_current=ERR_PASSIVE;
// When the receive or send error count returns to less than 127, the error status becomes active error
if((RxErrCountReg<127)&&(TxErrCountReg<127)) errstatus_current=ERR_ACTIVE;
}
if(can_irq & DOI_Bit)
{ // data overflow
CommandReg = (CDO_Bit|RRB_Bit);
return;
}
if(can_irq&EI_Bit)
{ // Error alarm interrupt, only bus close error is processed here
if(StatusReg&BS_Bit)
{ // Check the bus status bit of the status register
++busoff_counter;
ModeControlReg = 0x00;
return;
}
}
if(can_irq & RI_Bit)
{ // Receive data interrupt
if(StatusReg & DOS_Bit)
{
CommandReg = (CDO_Bit|RRB_Bit);
return;
}
can_readmsg();
return;
}
return;
}
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Next article:STM32 CAN---Error Management Analysis
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