GPIO block diagram of C6000 series DSP

火辣西米秀

GPIO block diagram of C6000 series DSP [Copy link]

First, take a look at the GPIO block diagram:

By looking at the GPIO block diagram, we can get a lot of information:

The DIR register controls whether the GPIO pin is input or output, where the corresponding bit is set to 0 to indicate that the pin is configured as an output pin; the corresponding bit is set to 1 to indicate that the pin is configured as an input pin.
If a GPIO pin is configured as Output, setting the corresponding position of the SET_DATA register to 1 will make the pin output a high level, and setting the corresponding position of the CLR_DATA register to 1 will make the pin output a low level. It should be noted that writing 0 to SET_DATA and CLR_DATA has no effect.
If a GPIO pin is configured as Input, the state of the pin can be obtained by reading the corresponding bit in the IN_DATA register. And writing 0 to SET_DATA and CLR_DATA has no effect.
If a GPIO pin is configured as Interrupt & EDMA event mode, the Input/Output configuration of the pin can be ignored at this time. The GPIO pin can be configured as interrupt/event trigger mode by setting the corresponding bits of the SET_RIS_TRIG and SET_FAL_TRIG registers. As shown in the following figure:

Since the C64+ CPU cannot directly access the RIS_TRIG and FAL_TRIG registers, if you want to access the configuration status of the interrupt mode, you can obtain it by reading SET_RIS_TRIG (SET_FAL_TRIG) or CLR_RIS_TRIG (CLR_FAL_TRIG).