STM32 CAN---Error Management Analysis

1 Several important concepts

       According to ISO11898, there are several important CAN-related definitions:

• Fault confinement

CAN nodes shall be able to distinguish short disturbances from permanent failures. Defective transmitting nodes shall be switched off. Switched off means a node is logically disconnected from the bus, so that it can neither send nor receive any frames.

CAN nodes can distinguish between normal errors and permanent faults. A faulty transmitting node will switch to the offline state. Offline means logically disconnected from the bus and can neither send nor receive.

• Error-active

An error-active node shall normally take part in bus communication and send an active error flag when an error has been detected. The active error flag shall consist of six (6) consecutive dominant bits and shall violate the rule of bit stuffing and all fixed formats appearing in a regular frame.

A node in the active error state can participate in the transmission and reception of bus communications normally and will send an error flag when an error is detected. The error flag consists of 6 consecutive display bits (these 6 consecutive display bits are different from the conventional fill bits and other frame fixed formats. Because of this, the hardware can easily distinguish them).

• Error-passive

An error-passive node shall not send an active error flag. It takes part in bus communication, but when an error has been detected a passive error flag shall be sent. The passive error flag shall consist of six (6) consecutive recessive bits. After transmission, an error-passive node shall wait some additional time before initiating a further transmission.

A node in the passive error state cannot send an active error flag. It can participate in normal communication, but when an error is detected, it sends a passive error flag. The passive error flag consists of 6 consecutive recessive bits. After the transmission is completed, the node in the passive error state needs to wait some extra time before sending again next time.

• Bus-off

A node shall be in the bus-off state when it is switched off from the bus due to a request of FCE. In the bus-off state, a node shall neither send nor receive any frames. A node shall start the recovery from bus -off state only upon a user request.

Due to the error boundary rules, a node may be offline, when in this state, the node neither sends nor receives. When to recover from offline depends on when the user requests it.

2 Incorrectly defined rules in ISO 11898

2.1 Description

When it comes to error demarcation, a node must be in one of the following three error states, depending on the node's error count value:

• Error-active

• Error-passive

• Bus-off

2.2 Error Count

The error counter will update the error count value when detecting the following events:

• When a receiving node detects an error, the error counter will be increased by 1. There is one exception, that is, when a single-bit error is detected when sending an active error flag or an overload flag.
• When a receiving node sends an error flag, the error counter is incremented by 8 when the first bit is detected as a dominant bit.
• When an error flag is sent after a transmission, the error counter is incremented by 8, except for two cases: 1: When the sending node is in an active error state and detects an ACK error caused by the absence of a dominant bit in the ACK field, but no passive error flag is detected during transmission; 2: When the sending node sends an error flag, a padding bit error is detected during arbitration (these padding bits should originally be recessive, but the detection result is dominant). The above two abnormal error count values ​​remain unchanged.
• When the sending node sends an active error flag or an overload flag, the error counter is incremented by 8 when a bit error is detected.
• When the receiving node sends an active error flag or an overload flag, the error counter is incremented by 8 when a bit error is detected.
• Any node shall tolerate 7 consecutive display bits when sending an active error flag, a passive error flag, or an overload flag. When 14 display bits are detected, or a passive error flag is followed by 8 display bits, or 8 consecutive dominant bits are detected followed by a passive error flag, all sending nodes increase their send error counter by 8, and all receiving nodes increase their receive error counter by 8.
• After successfully sending a frame of message, the sending counter should be reduced by 1, unless it is currently 0.
• After successfully receiving a frame of message, if the current receive counter value is greater than 1 and less than 127, the receive counter is reduced by 1; if the receive counter value is 0, it remains at 0; if it is greater than 127, the receive counter value should be set to a value between 119 and 127.

2.3 Transitions between active error state and passive error state

When the value of the send error counter or the receive error counter is greater than 127, the node changes to the passive error state.

When a node changes from an active error state to a passive error state, the node will send an active error flag.

When the values ​​of the send error counter and the receive error counter of the passive error node are both less than and equal to 127, it will change to the active error state again.

2.4 Offline Management

If the value of a node's send error counter exceeds 255, the node will be in offline state. A node in offline state will not have any impact on the bus. It will not send message frames, ACK, error frames, overload frames, etc. As for whether it will receive data on the bus, the implementation of this node is cancelled.

When a node in the offline state receives 128 connections with 11 recessive bits, it will become an active error state and set the send error counter and receive error counter to 0 at the same time.

Note: The specific implementation may not be exactly the same as described above. For example, in offline recovery, there is a switch in STM32 to set whether to automatically recover. If this function is disabled, then when the node in the offline state receives 128 connections and 11 consecutive recessive bits, it will not recover to the active error state.

Figure 1[page]

3 bxCAN implementation of STM32

3.1 bxCAN error status diagram

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3.2 Error Management

The error management described in the CAN protocol is completely implemented by hardware through the send error counter (TEC field in the CAN_ESR register) and the receive error counter (REC field in the CAN_ESR register), and its value increases or decreases according to the error situation. The software can read their values ​​to determine the stability of the CAN network. In addition, the CAN_ESR register provides detailed information on the current error status. By setting the CAN_IER register (such as the ERRIE bit), the software can flexibly control the generation of interrupts-when an error is detected.

3.3 Offline recovery

When TEC is equal to 255, bxCAN enters the offline state, and the BOFF bit of the CAN_ESR register is set to '1'. In the offline state, bxCAN cannot receive or send messages.

Depending on the setting of the ABOM bit in the CAN_MCR register, bxCAN can recover from the offline state (become an error-active state) automatically or at the request of the software. In both cases, bxCAN must wait for a recovery process described by the CAN standard (128 times 11 consecutive recessive bits are detected on the CAN RX pin).

If the ABOM bit is '1', the bxCAN will automatically start the recovery process after entering the offline state.
If the ABOM bit is '0', the software must first request the bxCAN to enter and then exit the initialization mode before the recovery process is started.

Note: In initialization mode, bxCAN does not monitor the state of the CAN RX pin, so the recovery process cannot be completed. In order to complete the recovery process, bxCAN must operate in normal mode.

4 CAN Error Status Register (CAN_ESR)

Address offset: 0x18
Reset value: 0x0000 0000

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