AT91SAM9261 Advanced Interrupt Controller (AIC)

AT91SAM9261 Advanced Interrupt Controller (AIC)
1.1 Description
     The Advanced Interrupt Controller (AIC) is an 8-level priority, independently maskable, vectored interrupt controller that can handle up to 32 interrupt sources. It is designed to substantially reduce software and real-time system overhead in handling internal and external interrupts.
     The AIC drives the nFIQ (Fast Interrupt Request) and nIRQ (Standard Interrupt Request) of the ARM processor. The inputs to the AIC come from internal peripheral interrupts or external interrupts from the product pins. The 8-level priority controller allows the user to define a priority for each interrupt source. This allows a high priority interrupt to be serviced even if a lower priority interrupt is being serviced. Internal interrupt sources can be programmed to be level active or edge triggered. External interrupt sources can be programmed to be rising or falling edge triggered or high or low active. The fast force feature redirects any internal or external interrupt source to a fast interrupt instead of a normal interrupt.
1.2 Block Diagram
Figure 1-1 Block Diagram1.3

Application Block Diagram
Figure 1-2 Application Block Diagram Description

Standalone Application	OS-based applications
	OS Driver	RTOS Drivers	Hard real-time tasks
		Generic OS interrupt handler
Advanced interrupt controller
Embedded peripherals		External peripherals (external interrupts)

1.4 Detailed AIC Block Diagram
Figure 1-3 Detailed AIC Block Diagram1.5

I/O Line Description
Table 1-1 I/O Line Description
Pin Name Pin Description Type
FIQ Fast Interrupt Input
IRQ0-IRQn Interrupt 0-Interrupt n Input1.6

Product Dependencies1.6.1
I/O Lines
    The interrupt signals FIQ and IRQ0 to IRQn are multiplexed through the PIO controller. Depending on the features of the PIO controller used in the product, the pins must be programmed according to the specific interrupt function. This does not apply when the PIO controller used in the product
is transparent in the input path.

1.6.2 Power Management
The Advanced Interrupt Controller is permanently clocked. The behavior of the Power Management Controller has no effect on the Advanced Interrupt Controller.
The output of the Advanced Interrupt Controller, nIRQ or nFIQ, when active, can wake up the ARM processor when it is in Idle mode. The general interrupt masking feature enables the AIC to wake up the processor without activating the processor's interrupt line, thereby synchronizing the processor to specific events.

1.6.3 Interrupt Sources
    Interrupt source 0 is always assigned to FIQ. If the product does not have a FIQ pin, interrupt source 0 cannot be used. Interrupt source 1 is always assigned to the system interrupt. This is the result of 'wired-OR' the interrupt lines of system peripherals such as the system timer, real-time clock, power management controller and memory controller. When a system interrupt occurs, the service routine must first determine the cause of the interrupt, which can be performed by successively reading the status registers of the above-mentioned system peripherals.
    Interrupt sources 2 to 31 can be connected to the interrupt outputs of embedded user peripherals or to external interrupt pins. External interrupt pins can be connected directly or through the PIO controller. The PIO controller is considered a user peripheral for interrupt processing. Accordingly, the PIO controller interrupt line is connected to interrupt sources 2 to 31. The peripheral
identifier defined at the product level is equivalent to the interrupt source number (which is also the bit number that controls the peripheral clock). Therefore, to simplify the description of functional operation and user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.