Understanding of MCU address space stack

    data – addressable on-chip RAM 0x00-0x7f
    bdata—bit-addressable on-chip RAM
    idata—addressable on-chip RAM, allowing access to all internal RAM 0x00-0xff
    padata—paged addressing to access external RAM
    xdata—addressable external RAM 0x0000- 0xffff
    code--program storage area The microcontroller memory is divided into ROM and RAM. RAM stores intermediate results, data and frequently changed codes, and ROM stores code. The 51 microcontroller uses a Harvard structure, that is, data and code have separate address spaces. The memory can be divided into program memory (eerom, flash, etc.), internal data memory (ram), SFR, bit address space and external data memory. The internal data memory is physically divided into internal SRAM and special function registers, and the internal is divided into low (0x00-0x7f) and (0x80-0xff), and the high 128 bytes of address are repeated, requiring different access methods. SFR uses direct addressing, and SRAM requires indirect addressing. Here SFR is a register, which is an internal component of the central processing unit in hardware and has a very fast access speed. In the lower 128B SRAM, 0x00-0x1f are 4 general working registers, each group has R0-R7. Which group to use can be configured through RS1 and RS0 in PSW. Bit addressing is at 0x20-0x2f. The
    program memory can be divided into several areas, stack area (stack), heap area (Heap), global area (static), text always bright area, program code area. After the program is compiled, global variables and static variables have been allocated memory space. When the function is running, the program needs to allocate stack space for local variables. When an interrupt comes, the function pointer also needs to be pushed into the stack to protect the scene so that it can return to the previously executed function after the interrupt is processed. The stack is allocated from high to low, and the heap is allocated from low to high. The stack we generally refer to is the stack. The stack is divided into hard stack and soft stack. The hard stack is SP, which grows from the top of the on-chip RAM downward. The soft stack is the space between the hard stack and the global variable area. The C51 function call is implemented through R0-R7 and the stack.
    Why does the bootloader not need to move the code from ROM to RAM when the microcontroller starts, while ARM does? Here we can first look at the process of microcontroller program execution. The microcontroller execution is divided into three steps: fetch and execute --- analyze instructions ---- execute instructions. The task of fetching instructions is: read instructions from the program memory according to the value of PC and send them to the instruction register. Then analyze and execute them. In this way, the microcontroller will fetch code instructions from the internal program memory and access related data from RAM. It should be known that the speed of RAM fetching is much higher than that of ROM, but because the microcontroller itself runs at a low frequency, it does not affect the slow fetching of instructions from ROM. ARM is different. The CPU runs at a high frequency, which is much greater than the speed of reading and writing from ROM. Therefore, there is generally an operating system, and part of the code needs to be copied to RAM before execution.