Design of high-speed serial port driver based on hash DMA

1 Overview

Since serial ports are widely used in telegraph communication, industrial control, data acquisition and other fields, most embedded processors have built-in universal asynchronous receiver-transmitters (UART). UART data transmission is mainly achieved through interrupts or DMA.

The interrupt mode is to generate an interrupt when data is received or needs to be sent, and read and write the UART buffer (FIFO) in the interrupt service program to realize data transmission. Since the serial port communication rate is generally low (typical value does not exceed 115 200 bps), most embedded systems use the interrupt mode to transmit serial port data. However, the interrupt service program needs to occupy CPU time, and the increase in serial port speed will inevitably cause the CPU to respond to UART interrupts more frequently, which is bound to cause the performance of the embedded system to decline.

DMA data transmission does not require the participation of the CPU and is a more efficient data transmission method. Existing DMA data transmission solutions are all based on DMA block transmission (i.e. Block DMA). In this way, a DMA interrupt is generated after each data block is transmitted. In high-speed serial communication, frequent DMA interrupts will still affect the performance of the system. This paper proposes a complete industrial-grade high-speed serial port driver design solution based on the hash DMA (seatter DMA) transmission method, which realizes UART data transmission with a baud rate of up to 12 Mbps.

2 Characteristics of DMA data transmission

DMA (Direct Memory Access) refers to the direct transmission of data between memory and I/O devices. Data operations are completed by the DMA controller (DMAC) without the participation of the CPU, which greatly improves the CPU utilization. Therefore, DMA is an ideal way to transmit high-speed data. When using DMA for data transmission, the following points should be noted:

① DMA transmission needs to occupy the system bus, during which the CPU cannot use the bus. If the peripheral cannot have any interruptions when performing data transmission, it is necessary to ensure that DMAC has exclusive use of the system bus during the transmission, which may affect other devices that need to use the bus for data transmission. Therefore, whether the system bus can be preempted during DMA transmission depends on the specific environment of the embedded system.

②DMA transmission has a cache coherency problem. As shown in Figure 1, DMAC and CPU are two parallel units. The CPU always accesses the data in the memory through the data cache, while the DMAC directly accesses the memory. If the data in the memory is updated by the DMAC, and the data in the data cache has not been updated, the values ​​of certain addresses obtained by the CPU may not be the real values ​​in the memory. To avoid this problem, the data cache can be refreshed after the DMAC updates the memory data or before the CPU reads the updated data, or a non-cacheable memory area that is not mapped by the data cache can be used.

DMA data transmission can be divided into two modes: block transmission and hash transmission. In the process of DMA data transmission, the source physical address and the target physical address must be continuous. However, in some computer systems (such as IA architecture), continuous memory addresses are not necessarily physically continuous, so DMA transmission must be completed in multiple times. After a block of physically continuous data is transmitted, an interrupt is triggered, and then the next block of physically continuous data is transmitted. This is the DMA block transmission mode (Block DMA). Hash transmission is developed on the basis of block transmission mode, and it is related to a transmission linked list, as shown in Figure 2. The linked list can be a one-way structure or a ring structure. The control word contains control information such as data bit width, data block size, and whether the current block transmission ends and triggers an interrupt. DMA block transmission can be regarded as a hash transmission containing only one node, and the next node pointer always points to the current node. The use of hash DMA mode can transmit data more flexibly and efficiently.

3 Implementing high-speed serial ports on the SPEAR300 platform

3.1 Hardware Platform

SPEAR300 is a high-performance embedded processor developed by ST based on the ARM926EJ-S core. Its maximum operating frequency is 333MHz, with 8 independent DMA channels and support for hash DMA; UART supports DMA transmission, the send and receive FIFO sizes are both 16 bytes, and the maximum baud rate supported at the 192 MHz peripheral bus (APB) frequency is 12 Mbps. If the APB frequency is increased, a higher baud rate can be obtained. The hardware platform of this article is a human-machine interface product with SPEAR300 as the core. The main peripherals include touch screen, LCD display module, network port and serial port (the serial port must support the Siemens MPI communication protocol with a maximum baud rate of 12 Mbps).

3.2 Driver Design

The core of the serial port driver is to achieve efficient and stable data transmission and reception. In order to achieve high-speed data transmission of UART, the UART interrupt is set to the highest priority; at the same time, interrupt nesting is allowed in the operating system, the UART receive timeout interrupt RTI is turned on, and the UART DMA transmission is enabled. In this way, when the UART transmit FIFO data is reduced to the set reference value (FIFOLevel), the transmit DMA transmission will be triggered. Similarly, when the receive FIFO data grows to the set value, the receive DMA transmission will be triggered. In order to reduce the number of DMA transmissions triggered and ensure that data is transmitted in time, the transmit FIFO Level is set to 2 bytes, and the receive FIFO Level is set to 14 bytes. There is a great risk to set the transmit and receive FIFO Levels to 0 and 16 bytes respectively. The MPI protocol requires that there should be no interruption in the transmission of a frame of data, so when using DMA to transmit UART data, the DMAC must monopolize the system bus. In order to avoid cache consistency problems, two non-cache memory areas are used to store the data to be sent and the data that has been received.

When sending data, the amount of data to be sent is always known. First, construct a transmission node, the data source address is the first address of the data packet, the destination address is the UART register, the data bit width is 8, and the next node pointer (PTR_NEXT) is empty. Before the current data packet is sent, if PTR_NEXT is updated, the transmission of the next data packet will automatically start. Whether the current data packet has been sent can be known by reading the TransferSize field of the DMAC register DMACCnControl. The entire process of sending data does not need to trigger any interrupts. The flow chart is shown in Figure 3. If the DMA block transfer method is used, a DMA interrupt needs to be generated after each transmission is completed, and the data needs to be reloaded into the send data area in the memory to send the next data packet.

When receiving data, the amount of data sent by the other party is generally unknown. Construct a circular linked list structure containing 100 nodes, and the transmission block size corresponding to each node is the receiving FIFO Level. The data source address is the address of the UART data register, and the destination address of the first node is the first address of the receiving data memory area. The destination address of the node thereafter shifts backward by (FIFO Level × 2) bytes each time, and the data bit width is 16 (8 data bits, 4 status bits, and 4 reserved bits). When the received data reaches 80% (RECV_TH) of the receiving memory area, it is necessary to notify the data sender to stop data transmission, and set a DMA interrupt at the 80th node, which is the threshold node. Using the design scheme of this article to receive 1 frame of data not exceeding the size of RECV_TH, at most one RTI interrupt is generated. When the amount of received data is less than FIFOLevel, DMA reception will not be triggered. In the RTI interrupt, the data in the UART receiving FIFO is copied to the data receiving area in the memory, and the destination address of the DMA receiving node is shifted backward by the corresponding length and the position of the threshold node is updated. The data receiving process is shown in Figure 4. If DMA block transfer is adopted, an additional ring data buffer (Ring Buffer) must be used. A DMA interrupt is generated each time a data block of a specified size is received, and the received data is copied to the ring data buffer in the interrupt service routine.

3.3 Driver Testing

The design scheme in this paper is directly applied to industrial HMI products and must undergo rigorous testing. A token network was built using three Siemens S7 series PLCs and one product prototype. The Siemens MPI protocol was used for testing, and the data analysis tool ProfiTrace was used to monitor the communication process. The test results show that stable data communication can be performed at various baud rates from 2400 bps to 12 Mbps.

Conclusion

This article introduces the characteristics of DMA data transmission and the working mode of hash DMA in detail. On this basis, a high-speed serial port driver design scheme based on hash DMA is proposed. The data transmission is completely completed by DMAC without triggering any interrupt. Receiving one frame of data that does not exceed the threshold of the receiving area will generate at most one RTI interrupt. Compared with various existing schemes that use DMA block transmission for serial port data communication, the number of interrupts is greatly reduced, which greatly improves the efficiency of data transmission. On the human-machine interface product that applies this scheme, stable data transmission with a baud rate of up to 12 Mbps is achieved. This scheme is a good reference for designing and implementing high-speed serial ports on other platforms.