Application of AT89C5131 in Interface Design

　　The structure of the USB2.0 full-speed slave interface of AT89C5131 is shown in Figure 3, which includes the USB D+/D- interface buffer, digital phase-locked loop, serial interface engine (SIE) and universal function interface (UFI). The digital phase-locked loop uses the clock of the microcontroller as input to generate the 48MHz clock required by other parts of the USB interface. The serial interface engine completes the encoding and decoding of the NRZI code of the USB communication physical layer, CRC generation, and verification and error correction. The universal function interface contains a dual-port data memory, one end of which is linked to the serial interface engine and the other end is connected to the microcontroller through the data bus, so that the microcontroller can complete the control and communication of the USB2.0 slave interface through special function registers.

　　1 System Hardware Design

　　The communication and control module based on AT89C5131 mainly completes the following functions: in terms of communication, it realizes communication with the computer through USB, receives the computer's control commands to the device and the data sent by the computer, and sends the working status of the device to the computer. At the same time, it transmits the control commands and data from the computer to other device modules through the SPI interface, and collects the status information of other device modules; in terms of control, AT89C5131 is responsible for collecting the control commands of the device control display panel, updating the device display status, etc. Due to the use of the USB communication system, AT89C5131 can control the operation of the device according to the control panel, and can also control the operation of the device according to the computer's commands, realizing dual control of the device. The peripheral connections of AT89C5131 in this system are shown in Figure 1. 

　　1.1 AT89C5131 Keyboard Port Characteristics and Keyboard Design

　　The AT89C5131 has a keyboard interface that allows connection to an 8×n matrix keyboard, and its inputs all have high or low level programmable interrupt capabilities. The communication between the keyboard interface and the C51 core is realized through three special function registers, namely the keyboard level select register (KBLS), the keyboard interrupt enable register (KBE) and the keyboard flag register (KBF).

　　The keyboard input of AT89C5131 is designed as 8 independent interrupt sources sharing the same interrupt vector. The interrupt enable bit KBD in register IEN1 allows the keyboard interrupt to be globally enabled or disabled. According to the value of each bit of KBLS, each keyboard input has the ability to detect a programmable level, and then the keyboard detection is reflected in KBF. The interrupt flag KBF can be masked by using KBE through software. It is this structure that allows the keyboard arrangement to be extended from a 1×n to an 8×n matrix, while also allowing the P1 input to be used for other purposes.

　　In this design, 4 keyboard ports (P1.O, P1.2, P1.3, P1.4) and 2 external interrupt ports (P3.2, P3.3) are connected to 6 buttons on the control panel to realize the system's internal and external, start and stop, pause and continue control and parameter group selection functions. These 6 ports are all triggered by low level to generate interrupts.

　　1.2 Characteristics of USB ports and USB communication design

　　The USB2.0 full-speed slave interface of AT89C5131 contains 7 terminal points, among which terminal point 0 is configured as the default control terminal point. The other terminal points 1 to 6 can be configured as control, burst, interrupt and periodic modes through special registers. Since each terminal point is controlled, identified and accessed by a set of independent registers, it is obviously not possible to accommodate these registers if they are directly mapped to the special function register address space of the 51 microcontroller. Therefore, the 7 groups of registers of these 7 terminal points actually use the same group of register addresses in the address space of the microcontroller, and a special function register (UEPNUM) is used to select which terminal point register group is actually selected by the current group of registers. This greatly saves the occupied address space and provides the possibility for integrating other special peripherals.

　　In this design, the PC transmits data to AT89C5131 via USB. After the data is transmitted once, AT89C5131 sends back a flag indicating whether the data transmission is correct or not. The PC can perform corresponding operations according to the received flag. The data transmitted from the PC to AT89C5131 are mainly of two types: parameters and control commands. To distinguish them, USB ports 4 and 6 are used to receive these two types of data. Among them, port 4 is used to receive control commands; port 6 is used to receive parameters. Accordingly, control commands are sent back using port 5; parameters are sent back using port 3. For simplicity, ports 3 to 6 are all configured as batch types; ports 3 and 5 are IN ports; ports 4 and 6 are OUT ports.

　　1.3 SPI port characteristics and SPI communication design

　　SPI (Serial Peripheral Interface) bus system is a synchronous serial peripheral interface, which enables MCU to communicate with various peripheral devices in serial mode to exchange information. SPI has three registers: control register SPCR, status register SPSR, data register SPDR. Peripheral settings FLASHRAM, network controller, LCD display driver, A/D converter and MCU, etc. SPI bus system can directly interface with a variety of standard peripheral devices produced by various manufacturers. The interface generally uses 4 lines: serial clock line (SCLK), host input/slave output data line MISO, host output/slave input data line MOSI and low-level effective slave select line SS (some SPI interface chips have interrupt signal line INT, and some SPI interface chips do not have host output/slave input data line MOSI). The full name of SPI interface is "Serial Peripheral Interface", which means serial peripheral interface. It was first defined by Motorola on its MC68HCXX series processors. SPI interface is mainly used in EEPROM, FLASH, real-time clock, AD converter, and between digital signal processor and digital signal decoder.

　　The SPI module of AT89C5131 allows full-duplex, synchronous, serial communication between MCU and other peripheral devices. It can provide programmable polarity and phase serial clock in two operating modes, either configured as master or slave, and also provides 8 programmable master clock rates. The SPI module includes 4 endpoints (MOSI, MISO, SCK, SS). MOSI and MISO are used to transmit data, and can only transmit 1 byte of data at a time. The difference is that MOSI outputs data from the master to the slave, while MISO is just the opposite. The SCK signal is used to synchronize the data input/output devices through MOSI and MISO. It can be driven by the host to generate 8 clock cycles to complete the exchange of a byte on the serial channel. SS is used for slave selection and is low effective. The configuration and initialization of the SPI module can be completed through the register SPCON, while the exchange of data requires the use of the registers SPSTA and SPDAT. In the process of software writing, whether the SPI can work properly depends mainly on the operation of the above three registers.

　　In this design, SPI is configured as host mode; the SS port is in an invalid state; AT89C5131 transmits parameters and control commands to DSP through the MOSI port; DSP sets the status of P1.1 (SS) port through software to indicate whether the data is received correctly, that is, if it is received correctly, P1.1 is set to 1, otherwise P1.1 is set to 0; AT89C5131 decides whether to retransmit the data by detecting the value of P1.1.

　　2 System Implementation

　　In order to realize the above design in engineering applications, on the basis of hardware design, software design of the interface is also required. The software design of AT89C5131 is mainly the design of USB firmware program. The software design is programmed in C language. Finally, the software is downloaded to the AT89C5131 chip through FLIP. The compilation environment used here is KeilμVision 3 software design platform. In the specific engineering implementation process, some problems were also encountered, but after repeated modifications and debugging, these problems have been well solved, mainly in the following aspects:

　　The key function of the control panel key is realized by level-triggered interrupt. At the beginning of the design, manually pressing a key will always trigger multiple interrupts, and the corresponding LED display will always jump quickly, which cannot meet the requirement of displaying a state after pressing a key once. So the author added a waiting function in the program for key function implementation, that is, after each interruption, it will wait for a period of time. After debugging, the above problem did not occur again.

　　The USB communication system requires that the USB can communicate quickly and efficiently. The speed problem can be solved by the Ping-pong mode. The system also requires that the USB can achieve two-way communication. In order to prevent the receiving and sending of data from interfering with each other, several ports are selected to achieve the transmission of different data.

　　SPI port communication The key to the realization of SPI port engineering is the matching of speed and working mode. At the beginning of the design, the SPI of AT89C5131 worked in slave mode, and its data transmission was controlled by DSP. Since its transmission speed was much lower than the processing speed of the SPI port in DSP, every time a set of data was transmitted through the SPI of AT89C5131, DSP always needed to wait for a long time through software control, and even so, it could not guarantee that the data would be received correctly. Therefore, the SPI working mode of AT89C5131 was later changed to host mode, and AT89C5131 actively controlled the transmission of data. However, the key to realizing two-way communication is the control of SS signal. In the above working mode, SS must be invalid so that Slave can reliably write data to the sending register.

　　3 Conclusion

　　AT89C5131 is suitable for forming a low-cost USB control and communication system, which can realize the communication between computers and devices, and can flexibly select a variety of communication protocols. This article introduces the interface design based on AT89C5131, which mainly realizes the communication between PC and MCU and MCU and DSP. This design has been applied in engineering practice. After practical verification, it has been proved that it is reasonable and flexible in operation, and has certain practical significance. During the design process, I deeply realized the great difference between hardware design and software design. After compiling the program source code correctly and without logical problems and burning it into the chip, the hardware circuit may not be able to fully realize the required functions, so it is necessary to repeatedly modify the program, burn, and debug until the function is correctly realized.