Theory and Application of DAC12 Module of MSP430 Microcontroller

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Theory and Application of DAC12 Module of MSP430 Microcontroller [Copy link]

1. Overview of Digital-to-Analog Conversion

The DAC12 module of MSP430 can convert the result of operation processing into analog quantity in order to operate the working process of the controlled object. The
DAC12 module of MSP430 is a 12-bit R-order, voltage output digital-to-analog conversion module. It can be set to 8-bit or 12-bit conversion mode during use
and can be used in conjunction with the DMA controller. When MSP430 contains multiple DAC12 modules, MSP430
can manage them in a unified manner.
The performance indicators of the DAC12 module of MSP430 are as follows:
[1] Resolution: This indicator reflects the change in analog output when the digital value in the lowest bit changes by 1. For a 12-bit DAC, its resolution
reaches 1/4096, that is, 0.025%.
[2] Offset error, which refers to the error of the output analog quantity to 0 when the input digital value is 0
[3] Linearity: refers to the maximum deviation between the actual transfer characteristic of the DAC module and the ideal straight line.
[4] Conversion speed: the number of conversions per second
[5] Other factors: such as digital input characteristics, input code, data format; output characteristics, whether the output is current or voltage; etc...

2. DAC12 Structure and Performance

The DAC12 module of the MSP430F169 microcontroller has two DAC channels, which are completely equal in operation.
The DAC12GRP control bit can be used to combine multiple DAC12 channels for synchronous updates, and the hardware can also ensure that the synchronous update is independent of any interrupt
or NMI event.
The main features of DAC12

• 8-bit, 12-bit resolution
• Programmable time-to-energy consumption
• Internal and external reference voltage selection
• Supports unsigned and signed data input
• With self-validation function
• Binary or two's complement form
• Multiple DACs synchronized update
• Direct access to memory

DAC12 schematic diagram

3. DAC12 register

[1] DAC12_xCTL DAC12 control register

The gray part can only be modified when DAC12ENC=0, and the bit DAC12GRP is only used in DAC12_1.
DAC12REFx: Select the reference source of DAC12
0, 1 Vref+
2, 3 Veref+
DAC12RES: Select DAC12 resolution
0 12-bit resolution
1 8-bit resolution
DAC12LSELx: Latch trigger source selection
When the DAC12 latch is triggered, the data in the latch can be transferred to the core of DAC12.
When DAC12LSELx=0, the DAC data update is not affected by DAC12ENC.
0 DAC12_XDAT will trigger when writing (regardless of the state of DAC12ENC)
1 DAC12_XDAT will trigger when writing (regardless of the state of DAC12ENC)
2 The rising edge of Timer_A3.OUT1
3 The rising edge of Timer_B7.OUT2
DAC12CALON: DAC12 calibration operation control
starts the calibration operation after setting, and is automatically reset after the calibration is completed. The calibration operation can correct the offset error.
0 No calibration operation is started
1 Start calibration operation
DAC12IR: DAC12 input range
sets the relationship between input reference voltage and output
0 The full scale of DAC12 is 3 times the reference voltage (AVcc is not operated)
1 The full scale of DAC12 is the reference voltage
DAC12AMPx: DAC12 operational amplifier setting
0 Input buffer off, output buffer off, high impedance
1 Input buffer off, output buffer off, 0V

2 Input buffer low speed low current, output buffer low speed low current
3 Input buffer low speed low current, output buffer medium speed medium current
4 Input buffer low speed low current, output buffer high speed high current
5 Input buffer medium speed medium current, output buffer medium speed medium current
6 Input buffer medium speed medium current, output buffer high speed high current
7 Input buffer high speed high current, output buffer high speed high current
DAC12DF: DAC12 data format
0 Binary
1 Binary complement
DAC12IE: DAC12 interrupt enable
0 Disable interrupt
1 Enable interrupt
DAC12IFG: DAC12 interrupt flag
0 No interrupt request
1 Interrupt request
DAC12ENC: DAC12 conversion control bit
DAC12ENC is valid only when DAC12LSEL>0.
0 DAC12 stops
1 DAC12 converts
DAC12GRP: DAC12 combination control bit
0 No combination
1 Combination

[2] DAC12_xDAT data register

The upper 4 bits of DAC12_xDAT are 0, which does not affect the operation of DAC12. If DAC12 works in 8-bit mode,
the maximum value of DAC12_xDAT is 0x00FF; when ADC12 works in 12-bit mode, the maximum value of DAC12_xDAT is 0x0FFF.

4. Operation of DAC12

[1] Select reference voltage

The reference voltage is the only analog parameter that affects the output of DAC12 and is an important part of the DAC12 conversion module. DAC12 can select internal
or external reference voltage, where the internal reference voltage comes from the 1.5V or 2.5V reference voltage generated by the internal reference voltage generator in ADC12
.
The time and power consumption of the DAC12 reference voltage input and voltage output buffer can be controlled by programming to achieve the best working state
(DAC12AMPx control).

[2]
The DAC12RES bit is used by the DAC12 core to select the 8-bit or 12-bit resolution of the DAC12. The DAC12IR bit controls the maximum output voltage of the DAC12 to be
1 or 3 times the reference voltage (without exceeding the power supply voltage). DAC12DF sets the format of the data written to the DAC12.

[3] Update the voltage output of DAC12

The DAC12 output pin is multiplexed with the breakout port P6 and the ADC12 analog input. When DAC12AMPx>0, regardless of
the status of the corresponding bits of P6SEL and P6DIR of the current port P6, the pin is automatically selected to the DAC12 function.
DAC12_xDAT can directly transfer data to the core of DAC12 and the two buffers of DAC12. The DAC12LSELx bit can trigger
the update of the voltage output of DAC12. When DAC12LSELx=0, the data latch becomes transparent. Regardless of the current
state of DAC12ENC, as long as DAC12_xDAT is updated, the core of DAC12 is immediately updated. When DAC12LSELx=1,
unless there is new data written to DAC12_xDAT, the data of DAC12 is always stored. When DAC12LSELx=2, 3,
the data is latched at the rising edge of the output signal TACCR1 of TA or TBCCR2 of TB. When DAC12LSELx>0,
DAC12ENC is used to enable the latch of DAC12.

[4] DAC12_xDAT data format

DAC12 supports binary or 2's complement input.

[5] Correct the output of DAC12

DAC12 has an offset error, and the offset can be automatically corrected by DAC12
. Before using DAC12, the offset correction operation can be initialized by setting the control bit DAC12CALON. After the operation is completed,
DAC12CALON will be automatically reset.

5. Application - Sine wave, triangle wave signal generator

  1 #include <msp430f169.h>
  2 /*
  3 * Software delay function
  4 */
  5 #define CPU_F ((double)8000000) //External high frequency crystal oscillator 8MHZ
  6 #define delay_us(x) __delay_cycles((long)(CPU_F*(double)x/1000000.0))
  7 #define delay_ms(x) __delay_cycles((long)(CPU_F*(double)x/1000.0))
  8
  9 #define uchar unsigned char
 10 #define uint unsigned int
 11 uchar k=0;
 12 uchar sin_table[256]={
 13 0x80,0x83,0x86,0x89,0x8d,0x90,0x93,0x96,0x99,0x9c,
 14 0x9f,0xa2,0xa5,0xa8,0xab,0xae,
 15 0xb1,0xb4,0xb7,0xba,0xbc,0xbf,0xc2,0xc5,0xc7,0xca,
 16 0xcc,0xcf,0xd1,0xd4,0xd6,0xd8,
 17 0xda,0xdd,0xdf,0xe1,0xe3,0xe5,0xe7,0xe9,0xea,0xec,
 18 0xee,0xef,0xf1,0xf2,0xf4,0xf5,
 19 0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfd,0xfe,
 20 0xff,0xff,0xff,0xff,0xff,0xff,
 21 0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xfd,0xfd,0xfc,
 22 0xfb,0xfa,0xf9,0xf8,0xf7,0xf6,
 23 0xf5,0xf4,0xf2,0xf1,0xef,0xee,0xec,0xea,0xe9,0xe7,
 24 0xe5,0xe3,0xe1,0xde,0xdd,0xda,
 25 0xd8,0xd6,0xd4,0xd1,0xcf,0xcc,0xca,0xc7,0xc5,0xc2,
 26 0xbf,0xbc,0xba,0xb7,0xb4,0xb1,
 27 0xae,0xab,0xa8,0xa5,0xa2,0x9f,0x9c,0x99,0x96,0x93,
 28 0x90,0x8d,0x89,0x86,0x83,0x80,
 29 0x80,0x7c,0x79,0x76,0x72,0x6f,0x6c,0x69,0x66,0x63,
 30 0x60,0x5d,0x5a,0x57,0x55,0x51,
 31 0x4e,0x4c,0x48,0x45,0x43,0x40,0x3d,0x3a,0x38,0x35,
 32 0x33,0x30,0x2e,0x2b,0x29,0x27,
 33 0x25,0x22,0x20,0x1e,0x1c,0x1a,0x18,0x16,0x15,0x13,
 34 0x11,0x10,0x0e,0x0d,0x0b,0x0a,
 35 0x09,0x08,0x07,0x06,0x05,0x04,0x03,0x02,0x02,0x01,
 36 0x00,0x00,0x00,0x00,0x00,0x00,
 37 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x02,0x02,0x03,
 38 0x04,0x05,0x06,0x07,0x08,0x09,
 39 0x0a,0x0b,0x0d,0x0e,0x10,0x11,0x13,0x15,0x16,0x18,
 40 0x1a,0x1c,0x1e,0x20,0x22,0x25,
 41 0x27,0x29,0x2b,0x2e,0x30,0x33,0x35,0x38,0x3a,0x3d,
 42 0x40,0x43,0x45,0x48,0x4c,0x4e,
 43 0x51,0x55,0x57,0x5a,0x5d,0x60,0x63,0x66,0x69,0x6c,
 44 0x6f,0x72,0x76,0x79,0x7c,0x80
 45 };
 46 /*
 47 * Clock configuration
 48 */
 49 void Clock_Init()
 50 {
 51 uchar i;
 52 BCSCTL1&=~XT2OFF; //Turn on XT2 oscillator
 53 BCSCTL2|=SELM1+SELS; //MCLK is 8MHZ, SMCLK is 8MHZ
 54 do{
 55 IFG1&=~OFIFG; // Clear oscillator error flag
 56 for(i=0;i<100;i++)
 57 _NOP();
 58 }
 59 while((IFG1&OFIFG)!=0); //If the flag is 1, continue to loop and wait
 60 IFG1&=~OFIFG;
 61 }
 62 /*
 63 * DAC12 initialization settings
 64 */
 65 void Init_DAC12()
 66 {
 67 ADC12CTL0 |= REFON + REF2_5V; //Internal reference voltage 2.5v
 68 DAC12_0CTL |= DAC12IR+DAC12AMP_5; //1 times reference voltage, medium speed current input and output,
 69 DAC12_0CTL |= DAC12ENC; //DAC12 enable
 70 DAC12_0DAT = 0x0000; //Assign initial value to DAC12_0DAT
 71 }
 72 /*
 73 * Triangle wave generating function
 74 */
 75 void Sanjiao()
 76 {
 77 uchar l;
 78 for(l=0;l<255;l++)
 79 {
 80 DAC12_0DAT=1;
 81 }
 82 for(l=255;l>0;l--)
 83 {
 84 DAC12_0DAT=1;
 85 }
 86 }
 87 /*
 88 * Cosine wave generator
 89 */
 90 void Sin()
 91 {
 92 DAC12_0DAT=sin_table[k++];
 93 delay_us(3);
 94 }
 95 /**
 96 * Main function
 97 */
 98 void main(void)
 99 {
100 WDTCTL = WDTPW | WDTHOLD; // Turn off the watchdog
101 P6SEL |= 0xFF;
102 P6DIR |= 0xFF;
103 Clock_Init();
104 Init_DAC12();
105
106 while(1)
107 {
108 Sin();
109 //Sanjiao();
110 }
111 }