Using CPLD to implement parallel communication between single chip microcomputer and ISA bus interface

CPLD (Complex Programmable Logic Device) is a complex user-programmable logic device. Due to its continuous connection structure, it is easy to predict delays, making circuit simulation more accurate. CPLD is a standard large-scale integrated circuit product that can be used in the design of various digital logic systems.

In recent years, due to the use of advanced integration technology and mass production, the cost of CPLD devices has continued to decline, and the integration density, speed and performance have been greatly improved. A single chip can realize a complex digital circuit system; coupled with easy-to-use development tools, the use of CPLD devices can greatly shorten the product development cycle and bring great convenience to design modifications [1]. This article takes the MAX7000 series of ALTERA as an example to realize the parallel communication between the MCS51 microcontroller and the PC104ISA bus interface. With this communication method, data transmission is accurate and high-speed. In the data acquisition system controlled by the MCS51 microcontroller with a 12MHz crystal oscillator, it can meet the requirements of real-time communication with the PC104 ISA bus interface, and the communication rate reaches 200Kbps.

1 Overall system design

Use CPLD to realize parallel communication between the microcontroller and the PC104ISA bus interface. Since PC104 mainly completes other data collection tasks and can only receive data sent by the microcontroller when it is idle, the real-time communication between the two parties is required to be very strong, but the amount of data is not very large. Therefore, in the system design, the microcontroller receives data in interrupt mode, and PC104 receives data in query mode. The system design scheme is shown in Figure 1. In the microcontroller part, D[0..7] is the data bus, A[0..15] is the address bus, RD and WR are the read and write signal lines respectively, INT0 is the external interrupt of the microcontroller, and when the external interrupt signal of the microcontroller is valid,

The microcontroller receives data. In the CPLD part, a PM7128 ESLC84 from the MAX7000 series is used to complete the data transmission, status query and delay waiting between MCS51 and PC104ISA bus interface. In the PC104ISA part, only the 8-bit data bus D[0..7] of PC104 is used, and A[0..9] is the address bus of PC104; /IOW and /IOR are read and write signals for the specified device; AEN allows DMA to control the address bus, data bus and read and write command lines for DMA transmission and read and write memory and I/O devices; IOCHRDY is the I/O ready signal, and the I/O channel is ready to high. At this time, the memory read and write cycle generated by the processor is 4 to 5 clock cycles. MCS51 inserts a wait cycle into the CPU by setting this signal to a low level, thereby extending the I/O cycle; SYSCLK is the system clock signal to synchronize the system with external devices; RESETDR is the power-on reset or system initialization logic signal, and is the system total clear signal.

2 Hardware implementation based on MAX+plusII

ALTERA's CPLD development tool MAX+plusII supports multiple input methods, which provides great convenience for design and development. Therefore, this system is designed using MAX+plusII. The main part of the system uses the schematic input method. Since the library provides ready-made chips, it is very convenient to use. The schematic input part is shown in Figures 2 and 3. Figure 2 mainly completes the data transmission and handshake judgment in the communication between the microcontroller and the ISA interface. In Figure 2, the signal descriptions are as follows: D[0..7] 8-bit bidirectional data bus of the microcontroller; PCD[0..7] 8-bit bidirectional data bus of the ISA interface; PCRD ISA interface read valid signal; PCWR ISA interface write valid signal; STATE ISA interface query selection signal, used to determine whether the microcontroller has written data or read data; PCSTATE microcontroller uses this to query the ISA interface to take away data; MCURD microcontroller read valid signal; MCUWD microcontroller write valid signal; INT0 microcontroller external interrupt signal. When the MCUWR signal is valid, the microcontroller latches the data in 74LS374 (1), and PCSTATE becomes high. PC104 uses the STATE signal to select 74LS244 to determine whether the data bit PCD0 is high. If it is high, it means that the microcontroller has sent data, then PCRD is enabled and the data is taken from the data latch 74LS374 (1). At this time, PCSTATE becomes low. The microcontroller determines that PC104 has taken the data by judging that this signal is low, and the next data can be sent.

When the PCWR signal is valid, PC104 latches the data in 74LS374 (2), and INT0 becomes low; the microcontroller generates an external interrupt, making the MCURD signal valid, and taking the data from the data latch 74LS374 (2). At this time, INT0 becomes high, and PC104 uses the STATE signal to select 74LS244 to determine whether the data bit PCD1 is high. If it is high, it means that the microcontroller has taken the data and can send the next data. The most critical issue for PC104 to communicate with the microcontroller is speed matching. Since the speed of PC104 is fast and the speed of the microcontroller is slow, a waiting cycle must be inserted at the IOCHRDY of PC104. As shown in Figure 3, the signal descriptions are as follows: IOCHRDY is used to make the ISA interface wait for 5 clock cycles; DLY_D delays the input signal; DLY_CL delays the waiting clock signal; DLY_CLR waits for the clear signal to prepare for the next data transmission; DELAY is the output signal after 5 clock cycles of delay, which is used as the input of the DLY_CLR signal; SYSCLK is the system clock signal of the ISA interface. During the communication between MCS51 and PC104, the DLY_D signal is always valid (high level). Under the action of the signal SYSCLK, the DELAY signal is valid once every 5 clock cycles, that is, it is high level. At this time, the DLY_CLR signal is valid (low level), the IOCHRDY signal becomes high level, and PC104 can read and write data. The address decoding part adopts text input method.

It is implemented using ALTERA's hardware design and development language AHDL (Altera Hardware Description Language). AHDL is a modular high-level language that is fully integrated into the MAX+plus II system and is particularly suitable for describing complex combinational logic, state machines, and truth tables. The address decoding part uses text input to fully demonstrate the advantages of text input. The text input content is as follows: SUBDESIGN Address (PCA[9..0]:INPUT; AEN, IOR, IOW: INPUT; RSETDR, DELAY: INPUT; A[15..14]: INPUT; RD, WR: INPUT; DLY_D: OUTPUT; DLY_CK: OUTPUT; DLY_CLR: OUTPUT; STATE: OUTPUT; PCRD: OUTPUT; PCWR ：OUTPUT; MCURD ：OUTPUT; MCUWR ：OUTPUT; ) BEGIN !DLY_CLR=RESETDR#DELAY; DLY_D=!AEN%26;amp;(PCA[9..1]= =H"110"); DLY_CK=!AEN%26;amp;(PCA[9..1]= =H"110")%26;amp;(!IOR#!IOW); !PCWR=!AEN%26;amp;(PCA[9..0]= =H"220")%26;amp;!IOW; !PCRD=!AEN%26;amp;(PCA[9..0]= =H"220")%26;amp;IOR; !STATE=!AEN%26;amp;(PCA[9..0]= =H"221")%26;amp;!IOR; !MCSWR=(A[15..14]= =H"2")%26;amp;!WR; END; Note: PCA[9..0] is the address signal of PC104, A[15..14] is the address signal of the microcontroller, and PC104 uses port addresses 220H and 221H.

3 Communication Software Design

PC104 is based on the ISA bus. Address conflicts must be avoided in system software design. PC104 uses address bits A0 to A9 to represent I/O port addresses, which means there are 1024 port addresses. The first 512 are used by the system board and the last 512 are used by the expansion slots. When A9=0, it represents the port address on the system board; when A9=1, it represents the port address on the expansion slot interface card [2]. Because this system uses reserved port addresses 220H and 221H, it is guaranteed that address conflicts will not occur.

In this program, PC104 uses the query method to receive data, and the microcontroller uses the interrupt method to receive data. #define pcreadwrite 0x220 ;PC104 read and write data port address#define pcrdstate 0x221 ;PC104 query status port address PC104 write data function: Void pcwrite(int port,unsigned char ch) { outportb(pcreadwrite,ch); while ((inportb(pcrdstate)%26;&;0x02)!=0x02) ;Wait for the MCU to read data{ } } MCU read subroutine: MCUR: MOV DPTR, #400H MOVX A, @DPTR RETI PC104 read data function: Unsigned char pcread(int port) { while ((inportb(pcrdstate)%26;&;0x0!=0x01) ;Wait for the MCU to write data{ } return inportb(pcreadwirte); } MCU write subroutine: MCUWR: MOV DPTR, #8000H MOVX @DPTR, A; Wait for PC104 to read and write data RET