DSP Learning (4) Bus Structure

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DSP Learning (4) Bus Structure [Copy link]

II. Bus Structure;
The bus structure of C5402 consists of 8 main 16-bit buses (4 program/data lines, 4 address lines):
· Program Bus (PB) Transfers instruction code and immediate operands from program memory.
· Three data buses (CB, DB, EB) Connect different internal parts, such as CPU, data address generation logic unit, program address generation logic unit, and on-chip peripherals. · Four address lines (
PAB, CAB, DAB, EAB) transmit the address required to execute instructions.
Using two auxiliary register arithmetic units (ARAU0, ARAU1), C5402 can generate two data memory addresses in one clock cycle. PB can store data operands in program space (such as coefficient table) to provide multiplier and adder for multiplication and accumulation operations, or store them in the target register of data space to provide data shift instructions (such as MVPD and READA). This capability, combined with the feature of reading two operands, supports the execution of single-cycle three-operand instructions (such as FIRS).
The C5402 DSP also has an on-chip bidirectional bus to access on-chip peripherals. The bus is connected to DB and EB through the bus switch in the CPU interface. Access through this bus requires two to three read or write cycles, depending on the structure of the peripheral.
III. Central Processing Unit (CPU);
40-bit arithmetic logic unit ALU. The C54X executes arithmetic instructions with a 40-bit arithmetic logic unit and two 40-bit accumulators (A and B). The ALU can also perform Boolean operations. Two 40-bit accumulators, accumulators A and B store the outputs of the ALU and the multiplication/addition module. They can provide a second input to the ALU, and accumulator A can be used as the input of the multiplication/addition module.
Serial shifter: The serial shifter of the C5402 has a 40-bit input, which is connected to the accumulator or data storage area (through CB or DB). It has a 40-bit output, which is connected to the ALU or data storage area (through EB). The serial shifter can shift the input data 0 to 31 bits to the left and 0 to 16 bits to the right.
17×17-bit multiplier: The fast on-chip multiplier allows the C5402 to efficiently perform operations such as convolution, correlation and filtering. In addition, the multiplier and ALU together can perform multiply-accumulate (MAC) operations and parallel ALU operations in one instruction cycle.
Compare, select, and store unit (CSSU): The compare, select, and store unit (CSSU) performs operations to compare the size of the high and low bits of the accumulator, allowing the detection/control bit TC in the status register ST0 and the transfer register (TRN) to keep their transfer records, and select the larger word in the accumulator to store in the data storage area.
IV. Memory structure;
Its memory is Harvard type and is divided into three independent addressing spaces; program, data, and I/O ports. It provides a total
address range of 192K words and can be expanded through enhanced peripheral interfaces. There are 16K DARAM and
4K P/D ROM on the C5402 chip. All storage spaces are divided into multiple 8K blocks, supporting paged addressing, which allows one block to be operated while another block is being operated, increasing processing speed.
1. On-chip memory;
the structure of the on-chip ROM (address: F800h--FFFFh): boot loader, 256-word μ-law extension table, 256-word A-law extension table, 256-word sin lookup table and interrupt vector table.
The structure of the on-chip DARAM (address: 0060h-3FFFh): divided into two 8K blocks.
The following CPU and peripheral storage mappings are on page 0 (0000h-007Fh).
· CPU memory storage mapping (0000h--000Fh)
This part includes: interrupt mask register, interrupt scalar register, status register ST0 and ST1, accumulator A and B, temporary register T, auxiliary register AR0-AR7, stack pointer SP, block loop address and counter register, processor mode register PMST and other registers related to CPU operation and status. The above 26 registers can be read and written without waiting for the state method.
· Peripheral memory storage mapping (0060h--003Fh)
This part controls the work of peripherals. By sending and receiving data between the registers of the mapping table and the peripherals, the bits of the control registers can be set to flexibly configure the peripherals, enable them, initialize them, etc.
· Program and data storage space (0060h-3FFFh)
The OVLY in PMST controls the on-chip RAM to be set as program or data space. When OVLY=0, the on-chip RAM is data space. When OVLY=1, RAM can be set as data and program space. The specific data and program space allocation is specified by the .cmd file and can be seen in the .map file.
Software programmable wait state generator: Extends the external bus cycle to 7 machine cycles to interface with slow memory or I/O devices outside the chip. The wait state generator does not work when there is no external hardware. For access to off-chip memory, the software programmable wait state generator (SWWSR) can specify 0-7 wait states, which applies to each program/digital memory and I/O space.
Programmable memory conversion logic: When the access process crosses the program or data memory boundary, the programmable memory conversion logic automatically inserts a cycle. When the storage process is transferred from program memory to data memory, a cycle is also inserted. This additional cycle allows the memory to release the bus before other devices start driving the bus to avoid bus contention. The size of the converted memory bank is determined by the memory bank conversion register (BSCR).
2. Addressing mode
· Single operand addressing, single operand address modification;
· ARAU and address generation operation;
two auxiliary register operation units ARAU0 and ARAU1 operate on the contents of the auxiliary register (16-bit unsigned number), and the required address can be obtained by pre-changing the value of the auxiliary register.
C5402 DSP has seven basic addressing modes:
1: Immediate addressing:
1) Short immediate addressing length can be 3, 5, 8, or 9 bits.
2) 16-bit immediate addressing, which structure to use depends on which instruction is used.
2: Absolute addressing:
1) dmad (data storage area addressing), define the register label in the data space, and then read and write operations can be performed on the memory pointed to by the label.
2) pmad (program storage area addressing).
3) PA (port addressing) addressing, direct reading and writing of ports.
4) *(lk) addressing means that any address in the data space can be addressed without changing DP or SP, but it cannot be used for RPT and RPTZ instructions.