Design and implementation of intelligent controller for high-speed real-time data acquisition

0 Introduction

Since the early 1970s, the birth of microprocessors has promoted the rapid development and application of computer information technology. Data acquisition and processing is a combination of intelligent sensor systems, signal acquisition conditioning and conversion, computer information and other technologies, and is an important means of obtaining information. With the popularization of microprocessors, data acquisition technology plays an increasingly important role in the industrial field.

Traditional data acquisition equipment controllers are mainly based on single-chip microcomputers and PCs. The former has limited data processing capabilities and poor real-time performance; the latter has high costs and poor flexibility. ARM microprocessors have the advantages of small size, low cost, and rich functions. FPGA has a parallel computing structure and rich I/O resources, and has obvious advantages in high-speed real-time data processing. The ARM+FPGA system architecture can combine the advantages of both to achieve high-speed real-time data acquisition and processing.

ARM and FPGA work in master-slave mode. The main processor ARM uses AT91SAM9260 from ATMEL, USA, which can achieve 200MIPS processing performance when the main frequency is 180MHz.

The FPGA used in the device is the Altera Cyclone series EP1C6Q240I8N FPGA. The FPGA working clock is 50MHZ, and the working clock can be multiplied by setting the internal phase-locked loop.

1 System Overall Plan

The intelligent controller is mainly composed of three parts: ADC data acquisition circuit, FPGA minimum system, and ARM minimum system. The ADC uses a single-power supply 14-bit AD9240 with a sampling rate of up to 10 MSPS. It uses a high-speed, low-cost CMOS process, and its resolution and speed have reached the level of existing hybrid solutions, while its power consumption and cost are much lower. The coprocessor uses ALTERA's EP1C6O240I8N chip, and the FPGA minimum system is formed by connecting two 32KB SRAM memories, a 4Mbit serial configuration chip EPCS4, a standard AS programming interface, and a JTAG debugging interface. The ARM minimum system consists of an AT91SAM9260 microprocessor, a 64MBytes SDRAM and a 256MBytes NandFlash for running and storing programs, an RS232 interface, and a 10/100-Base-T Ethernet interface.

The working principle of the system is: first, the two signals from the signal acquisition and conditioning circuit are sent to two ADCs for synchronous sampling, and the ADC converts the analog signal into a digital signal with 14-bit precision; then the FPGA pre-processes the digital signals converted by the ADC of the two channels, and uses the multi-point sampling and averaging method to filter out the 50Hz power frequency interference; finally, the two ADC sampling data are stored in two SRAM caches. ARM and FPGA communicate using the data bus. By developing a character-type FPGA device driver under the Linux operating system and then compiling or loading it into the Linux kernel, ARM can read the data pre-processed by the FPGA in the application layer program. At this time, the FPGA directly connects the ARM bus to the SRAM bus to read the data pre-processed by the FPGA. ARM can communicate with the host computer through Ethernet and RS232 interfaces.

2 ARM and FPGA communication interface design

The core board where the main processor ARM is located is responsible for the control and management of the entire system. The communication interfaces of the intelligent controller and the host computer, serial port, Ethernet, and CAN, are derived from this board. The communication between the core board and the expansion board coprocessor FPGA adopts bus mode. The essence of this communication mode is that FPGA acts as the peripheral SRAM of ARM, and ARM accesses the memory for read and write operations. The connection is shown in Figure 2.

ARM is connected to FPGA through a bus. ARM's data lines D0:D15, address lines A1:A14 and chip selects NCS4 and NCS5 are connected to FPGA. The other two SRAMs are directly connected to FPGA. NCS4 controls the reading and writing of FPGA internal status registers and command registers. NCS5 controls FPGA to read and write data stored in the two SRAMs. All data information is transmitted through the DATA[0:15] bidirectional data bus.

The NCS4 chip select valid address corresponding to the ARM address mapping is 0X5000 0000-0X5000 8000, and the NCS5 chip select valid address corresponding to the ARM address mapping is 0x60000000-0x6000 8000. At this time, the FPGA is essentially equivalent to the ARM internal memory. Any address in the address range is selected as the FPGA internal register address for ARM and FPGA communication. These registers are written to the FPGA by ARM, and read from the FPGA by ARM.

If the main processor ARM wants to directly read the ADC sampling pre-processed data stored in the two SRAMs from the address range of 0X6000 0000-0x6000 8000, it needs the assistance of the coprocessor FPGA.

This clarifies the tasks that the coprocessor FPGA needs to complete when communicating with the main processor ARM: 1) parse the commands of the main processor ARM to write to the FPGA register and execute the corresponding operations; 2) write some status information after the operation is executed into the corresponding FPGA internal register for the main processor to query the operation results; 3) assist and cooperate with the main processor ARM to read the ADC acquisition pre-processed data stored in the two SRAMs.

3 System Software Design

The intelligent controller software includes Linux FPGA character device driver, main processor ARM application, FPGA data collection and preprocessing storage program. The software system structure diagram is shown in Figure 3.

3.1 FPGA Device Driver

Linux device drivers are divided into three categories: character devices, block devices, and network devices. Character devices are devices that input and output data in characters. The FPGA device driver is a character device driver, and its basic framework is: 1) define a structure static structfile operations variable, which defines some device opening, closing, reading, writing, and control functions; 2) implement these functions defined in the structure outside the structure; 3) register or delete the driver module in the kernel. In the Linux kernel, a character device uses the cdev data structure to describe and manage device files. The coprocessor FPGA of the intelligent controller is used as the external static memory SRAM of the main processor ARM. Therefore, the main processor ARM can generate signals through the static memory controller (SMC) to control the external storage device or peripheral interface device to perform read and write operations. The FPGA character device driver can complete the control of the FPGA module and complete data acquisition. The most critical thing is to initialize the FPGA module and configure the SMC of the main processor ARM to realize the FPGA bus driver. You can refer to the read and write timing of the ARM static memory controller.

From the above figure, we can see that the main configuration of the static storage controller is SMC_SETUP, SMC_PULSE, SMC_CYCLE, SMC_MODE. The configuration is implemented through the function static inline void at91_sys write(unsigned intreg_effset, unsigned long value). The detailed configuration is as follows:

at91_sys_write(AT91_SMC_SETUP(5),AT91_SMC_NWESETUP(0x02)|AT91_SMC_NCS_WRSETUP_(0x00)|AT91_SMC_NRDSETUP_(0x00)|AT91_SMC

_NCS_RDSETUP_(0x00));

at91_sys_write(AT91_SMC_PULSE(5),AT91_SMC_NWEPULSE_(0x06)|AT91_SMC_NCS_WRPULSE(0x0A)|AT91_SMC_NRDPULSE(0x0A)|AT91_SMC_ NCS_RDPULSE_(0x0A));

at91_sys_write(AT91_SMC_CYCLE(5),AT91_SMC_NWECYCLE_(0X0A)|AT91_SMC_NRDCYCLE_(0X0A));

at91_sys_write(AT91_SMC_MODE(5),AT91_SMC_READMODE|AT91_SMC_

WRITEMODE|AT91_SMC_EXNWMODE_DISABLE|AT91_SMC_DBW_16|AT91_ SMC_TDF_(1));

Apply for I/O memory:

request_mem_region((unsigned long)sram_buf_1, SRAM_BUFSIZE, "fpga_arm");

request_mem_region((unsigned long)sram_buf_2, SRAM_BUFSIZE, "fpga_arm");

FPGA register address mapping:

sram_buf_1=(unsigned char*)ioremap(0x60000000, SRAM_BUFSIZE);

sram_buf_2=(unsigned char*)ioremap(0x60004000, SRAM_BUFSIZE);

The above is the most critical configuration for initializing the FPGA character device driver. The rest is to write the driver function under the file operation structure. Each member in the structure except owner must point to the function in the driver. The most important kernel state function is staticssize_t fpga_arm_read(struct file*filp，char_user*buf,size_tsize，loff_ t*ppos), which corresponds to the application layer function read. The driver uses the readw function to read data from the FPGA to complete the reading of 16-bit data from the memory-mapped I/O space. copy_to_user(buf, (void*)(read_mem), size) copies data from the kernel space to the user space. The FPGA character device driver basically realizes the control and management of the FPGA reading status information and the data collected by the two ADCs.

3.2 Coprocessor FPGA Control Program

The coprocessor FPGA control program is divided into three parts: control ADC data acquisition module, control read and write SRAM module and FPGA and ARM bus communication module. The FPGA and ARM bus communication module is located in the top module, and the control ADC data acquisition module and control read and write SRAM module are the bottom modules. The top module mainly instantiates the bottom module and then performs digital signal synthesis processing.

Controlling the ADC data acquisition module and parallel ADC is relatively simple. The clock driving ADC CLK is required for normal operation. When writing the ADC sampling program, the most important thing is to pay attention to reading the collected data on the rising edge of ADC CLK to ensure stability and reliability. FPGA will pre-process the data collected by the two ADCs by multi-point averaging, mainly to filter out the 50Hz power frequency interference, and then write it into SRAM for storage.

Control the read and write SRAM module. The FPGA write SRAM and read SRAM operations are very similar. The SRAM model is CY7C1021DV33. The chip select signal CE should be pulled low during operation. When reading, pay attention to the OE signal being pulled low first and then high. On its rising edge, read the data. When writing, pay attention to the WE signal being pulled low first and then high. On its rising edge, write the data. When reading SRAM from FPGA, you need to pay attention to sram_cs (chip select), sram_oe (read control), sram_addr (address line) and sram1_data (16-bit data line). Pull sram_cs and sram_oe low at the same time, and assign a value to the address line sram_addr. After one clock, the data on the data port sram_data is valid.

The communication module between FPGA and ARM is relatively complex. First, ARM sends control commands to FPGA. The important signals when ARM writes to the internal register of FPGA are: NCS4 (chip select), at9260_wr (write signal), at9260_addr (address line), at9260_data (data line). When NCS4=0&&at9260_wr=0, it means that ARM9260 is writing to the FPGA register. The specific register is determined by the address signal at9260_addr, so that at9260_data can be written to the corresponding register at the corresponding address.

Secondly, ARM reads the FPGA internal status register, which is very similar to ARM writing the FPGA register. When NCS4=0 &&at9260_rd=0, it means that ARM9260 is reading the FPGA register. At this time, we assign the register value to at9260_data. at9260_data is a bidirectional IO and needs to be set to high impedance when not reading.

Finally, ARM obtains the pre-processed data stored in the two SRAMs. The control signals of ARM are NCS5, at9260_rd, at9260_addr, and A14. FPGA converts these signals into FPGA reading SRAM signals, and then transmits the data read by FPGA to ARM. Here, FPGA plays the role of data transfer.

3.3 Main Processor ARM Application

The application of the main processor ARM is the control core of the entire software system. The application consists of two threads: main thread and data_recv thread. The main thread is mainly used to create threads and send control commands to the FPGA; the data_recv thread receives the FPGA status information and the data collected by the ADC after FPGA preprocessing. The application controls and manages the coprocessor FPGA device through the file descriptor fd_fpga. Because the operating system Linux is ported to the main processor ARM, and the kernel version is Kernel 2.6.30, the application is developed under the Linux operating system Ubuntul2.04 LTS version, and the development software used is Eclipse C/C++. Set Eclipse to use the cross compiler arm-none-linux-gnueabi-gcc and Release configuration to generate a binary executable file. Then it can be downloaded to the target board through the Tftp service.

4 Conclusion

This article discusses the design and implementation of a high-speed real-time data acquisition intelligent controller based on the ARM+FPGA architecture. It combines the advantages of both ARM and FPGA, has better computing and processing performance, and a rich set of peripheral standard interfaces. The system sampling rate reaches 10MSPS, meeting the requirements of high-speed real-time performance. It has high application value.