Design of high-speed and high-precision pipeline analog-to-digital converter

　　With the advent of a new generation of wireless mobile communications, digital intermediate frequency receivers in communication systems have increasingly higher requirements for ADC speed and accuracy, and pipeline ADCs that take both speed and accuracy into account are a better choice to meet this requirement.

　　In the design of large-scale analog circuits, due to the large scale of the circuit, if the parasitic resistance is extracted when extracting parasitic parameters, the number of circuit nodes will increase sharply, and the subsequent simulation speed will be very slow or even unable to converge. Therefore, when extracting parasitic parameters, generally only parasitic capacitance is extracted, so that the number of circuit nodes will not increase and the simulation time will not be too long. However, when this method is used, the simulation will ignore the influence of parasitic resistance, which is different from the actual situation and needs to be considered in the layout design, especially when static current flows in the layout routing.

　　This paper presents the test results of two tape-outs. It focuses on analyzing the influence of the parasitic resistance on the wires on the ADC reference voltage, static characteristics, and dynamic characteristics due to unreasonable wiring during the design of the reference voltage module layout of the first version of the chip, and uses MATLAB to build a behavioral model of the pipeline ADC to simulate and verify the influence of parasitic resistance on ADC performance. In addition, based on the analysis of the test results of the first version of the chip, the layout of the reference voltage generation circuit of the second version of the chip was corrected and then re-taped. The test results show that the analysis of parasitic resistance is reasonable and the corresponding correction measures are effective.

　　System structure and key circuit module design

　　The system structure of the pipeline ADC is shown in Figure 1, which mainly consists of three parts: clock circuit, reference circuit and ADC core circuit. The ADC core circuit uses a sample-and-hold amplifier (SHA) to collect analog input signals, and then the first stage adopts a 3.5-bit/stage structure, the next 7 stages adopt a 1.5-bit/stage structure, and the last stage is a 2-bit ash ADC.

　　Sample and Hold Amplifier

　　If the sample-and-hold amplifier is not used, the input bandwidth of the ADC will be limited by the aperture error [1], so this design places a SHA before the stage circuit. Considering both noise and power consumption, the SHA adopts a charge flip-around structure instead of a charge redistribution structure.

　　Optimization of level resolution

　　When the first-stage circuit enters the settling phase from the sampling phase, a step voltage Vx is generated at the input of the op amp. Reference [2] points out that the higher the resolution of the first-stage circuit, the smaller the step voltage Vx, which means the shorter the settling time and the lower the requirement for the op amp slew rate. The improvement of the first-stage circuit resolution can reduce the requirements for capacitor matching [3], so that a 12-bit ADC can be realized without calibrating the capacitor mismatch. In addition, compared with the 1.5-bit/stage structure, the 3.5-bit/stage structure has more advantages in power consumption and area.

　　Stage reduction technology

　　As the system's requirements for accuracy at each level are gradually reduced, the speed and gain of the op amp can also be reduced step by step, so the power consumption and area of ​​the op amp can also be reduced step by step, which reduces the total power consumption and area of ​​the ADC. In addition, the dynamic charging and discharging of the capacitor during the operation of the MDAC causes a part of the dynamic power consumption, so the power consumption can also be reduced by gradually reducing the capacitance value while meeting the KTC noise requirements. While reducing the capacitance, the load of the op amp is actually reduced, thereby further reducing the power consumption of the op amp.

　　Operational Amplifier

　　High-precision ADCs have very high requirements for the gain of the op amp. For the SHA of a 12-bit ADC, the error caused by the limited DC gain is required to be less than 1/2 LSB, that is:

　　Where N is the resolution of the ADC, Cp is the parasitic capacitance at the input of the op amp, and Cs is the sampling capacitor. Assuming Cp/Cs<<0, A0 must be at least greater than 78dB. Considering the process deviation, at least 6dB of margin should be left during design, which means A0 must be greater than 84dB. In the 0.18mm CMOS process, the intrinsic gain is relatively small, and it is difficult to achieve such a large gain using a general structure. We choose the structure shown in Figure 2. The first stage is a common source and common gate structure with gain bootstrapping technology [4], which is mainly used to achieve high gain. The second stage is a simple common source amplifier, which is mainly used to achieve a large output swing.

　　Bootstrap Switch

　　In CMOS circuit design, commonly used switches include MOS tube single-tube switches, transmission gate switches (CMOS complementary switches) and gate voltage bootstrap switches [5]. Since single-tube switches and transmission gate switches will introduce serious nonlinearity when connecting signals with large amplitude changes, and gate voltage bootstrap switches have good linearity, the sampling switches in the sample-and-hold amplifier, the first-stage circuit and the second-stage circuit all use gate voltage bootstrap switches to improve the linearity of the ADC. Since the sampling switches in the subsequent stages are required to be gradually reduced, simple CMOS complementary switches can be used. Test results and analysis of the first version of the chip [page]

　　When the input signal frequency is 2.41MHz and the amplitude is close to 2Vp-p, the sampling rate increases from 15.5MHz to 100MHz, and the SNDR and SFDR of the ADC are greater than 57.9dB and 68.9dB respectively. In addition, the DNL of the chip is measured to be -1.0/+0.2LSB, and the INL is -5.0/+5.0LSB.

　　As shown in Figure 3 (a) and (c), they are the INL and FFT curves measured at a 30MHz sampling rate and a 2.41MHz input signal. The INL is -5.0/+5.0LSB, the SFDR is 68.9dB, and the SNDR is 58.4dB. Whether it is dynamic performance or static performance, this result is obviously not satisfactory for a 12-bit ADC. By observing the static characteristic curve, it can be found that the curve is very regular, with an inflection point every 256 codes. This is because there is a missing code phenomenon every 256 points. There are 14 missing codes in total, which coincides with the broken line position of the ADC's first-stage 3.5-bit transmission curve. Therefore, it is inferred that there may be a problem with the first-stage circuit.

　　Through careful analysis of the layout, a serious problem was found in the layout. As shown in Figure 4, the reference voltage generation circuit uses a two-stage op amp with an open-drain structure for the buffer circuit of Vrp and Vrn. A group of resistors are connected in series between the buffers of Vrp and Vrn to generate the 14 comparison levels required by the 3.5-bit flash ADC in the first-stage circuit. If parasitic resistance is not considered, nodes 1 and 2 are coincident, and the reference voltage VRP' of the first stage is equal to the reference voltage VRP of other stages, and the same is true for VRN and VRN'. However, since the wires have resistance, the actual situation is that there is a parasitic resistance Rp between nodes 1 and 2, and between 3 and 4, and the driving circuits of Vrp and Vrn are both open-drain structures. There is a static current Idrop between nodes 1 and 4. This current flows through Rp and causes a voltage difference between nodes 1 and 2:

　　The situation between nodes 3 and 4 is the same. The estimated value of Rp is about 8.5Ω, and Idrop is about 0.76mA, so V is 6.5mV. When drawing the layout, the influence of parasitic resistance was not considered, and the reference voltage for the DAC of the first stage circuit was directly drawn from nodes 2 and 3. As a result, the reference voltage VRP' and VRN' of the first stage differed by V from the reference voltage VRP and VRN of the following stages. Therefore, the reference voltage of the first stage circuit is:

　　The reference voltage of the following circuits is:

　　Since the reference voltage of the first stage circuit is smaller than that of other stages, the ADC has missing codes. In order to further analyze the impact of the small reference voltage of the first stage on the static and dynamic characteristics of the ADC, we use Matlab to perform behavioral modeling simulation and compare the INL, SFDR and SNDR at a 30MHz sampling rate.

　　The modeling is mainly based on the following two premises:

　　(1) The reference voltage of the first level is: Vref'=0.987V

　　The reference voltage of other levels is: Vref=1V

　　(2) Non-ideal factors such as noise, mismatch, limited gain and limited bandwidth of the op amp are not considered.

　　As shown in (b) and (d) of Figure 3, the ADC behavioral level simulation results are shown. The INL of the behavioral level simulation is -4.2/+4.4 LSB, the SFDR is 65dB, and the SNDR is 59.2dB. It can be seen from the figure that the simulation results reproduce the actual test results very well. The small first-level reference voltage not only aggravates the odd-order harmonic distortion of the ADC, but also causes a large even-order distortion. In general, the small first-level reference voltage will have a great impact on the static and dynamic characteristics of the ADC. The simulation better explains why the static and dynamic characteristics of the ADC are very poor during actual measurement.

        Improvements and test results of the second version of the chip

　　The second version of the chip has modified the layout of the reference voltage circuit of the first version of the chip, as shown in Figure 5. Originally, the reference voltage of the first-level DAC was introduced from nodes 2 and 3, but now it is changed to be connected from the reference voltage of the second level, that is, from nodes 1 and 4, so that the reference voltages of the DACs of each level of the ADC circuit are equal.

　　As shown in Figure 6, at a 15.5MHz input signal frequency and a 20MHz sampling rate, the DNL and INL are measured to be -0.22/+0.21LSB and -0.62/+0.46LSB respectively.

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　　Figure 7 is a 32768-point FFT spectrum measured at 15.5MHz input and 100MHz sampling rate. It can be seen from the figure that the SFDR reaches 79.8dBc, the SNDR is 65.1dB, and the effective number of bits ENOB is 10.5bit.

　　Figure 8 shows the values ​​of SFDR and SNDR as the sampling rate changes. When the input signal is 2.41MHz, the SFDR remains above 86dBc in the 100MHz sampling rate range, and the ENOB is greater than 10.9bit. For the 15.5MHz input signal, the SFDR remains above 78dBc, while the ENOB drops from 10.8bit at 50MHz sampling rate to 10.5bit at 100MHz sampling rate.

　　Figure 9 is a micrograph of the chip, and Table 1 lists the key indicators of the second version of the chip. Comparing the test results of the two versions of the chip before and after the layout correction, we can find that the INL of the ADC after the correction is reduced from the original -5.0/+4.8LSB to -0.62/+0.46LSB, and the SNDR and SFDR are increased from the original 57.9dB and 68.9dBc to 67.5dB and 87.2dBc at 2.41MHz input and 100MHz sampling rate. Therefore, the analysis of parasitic resistance in this article is reasonable, and the corresponding correction measures are also effective.

　　Conclusion

　　This paper presents the test results of two tape-outs, focusing on the analysis of the reasons why the performance of the first version of the chip was not ideal, pointing out that the problem lies in the parasitic resistance effect in the layout design, and using MATLAB behavioral modeling to verify the impact of this effect on the ADC performance. According to the analysis results, the second version of the chip layout was modified accordingly and tape-out again. The test results show that the analysis of parasitic resistance in this paper is reasonable and the corresponding correction measures are effective. After correction, the INL of the ADC is reduced from the original -5.0/+4.8 LSB to -0.62/+0.46 LSB; at 2.41MHz input and 100MHz sampling rate, the SNDR and SFDR are increased from the original 57.9dB and 68.9dBc to 67.5dB and 87.2dBc respectively. The ADC is processed in 0.18mm CMOS process, with a total area of ​​3.51mm2, a power supply voltage of 1.8V, and a power consumption of only 112mW.