Design and implementation of intelligent detector based on 89C56

1 Introduction
In recent years, with the development of computer, microelectronics, communication and network technology, people have put forward higher and higher requirements on the reliability, volume, power consumption and other aspects of equipment, especially in some cutting-edge fields, strict requirements are put forward on various parameters and indicators of equipment. In the development process of a large-scale equipment, according to the design requirements, high-precision stable voltage is required. If the voltage is unstable or there is a noise signal, early warning measures need to be provided. Therefore, in addition to the need to design the voltage stabilizer well and provide good and complete filtering and denoising functions, a dedicated noise detection module needs to be designed. In response to this demand, this paper proposes a design and implementation scheme of an intelligent noise voltage detector based on a high-performance microcontroller.

In terms of hardware, the intelligent detection system is built with a microcontroller as the core and a collection of various commonly used components as the basic elements to construct the hardware design and detection system.

2 Overall design of intelligent detector
The intelligent detector is based on the high-speed microcontroller 89C56, and expands the memory, signal acquisition module, voltage comparator, power supply circuit and other modules to form a basic board-level system. Its logical structure is shown in Figure 1.

Figure 1: Overall structure of intelligent detector

The detector first obtains the voltage signal from the target system through the signal acquisition module, and then compares the obtained voltage signal with the preset voltage value through the voltage comparison module to determine whether there is noise in the current voltage signal and what the noise value is accurately. If the noise value exceeds a certain range, the signal is converted from analog to digital through the A/D conversion module and handed over to the core processor for processing.

In the actual circuit, the DAC uses a 12-bit converter integrated in the microcontroller C8051F020. The output swing of the DAC on the chip is 0V to VREF-1LSB, and the corresponding input code range is 0x000 to 0xFFF, which can be enabled or disabled using the corresponding control register. When disabled, the output of the DAC remains in a high-impedance state, and the supply current drops to 1µA or less. It has a flexible output update mechanism that allows seamless full-scale changes and supports jitter-free output updates. In default mode, the output of the DAC is updated when the high byte (DACxH) of the DAC data register is written. When writing DACxL, the data is held and has no effect on the DAC output until a write operation to DACxH occurs. If a 12-bit word is written to the DAC data register, the 12-bit data word is written to the low byte (DACxL) and high byte (DACxH) data registers. The data is latched into the DAC after writing the DACxH register. The DAC can be used in 8-bit mode, in which case DACxL is initialized to a desired value (usually 0x00) and data is written only to DACxH. The DAC output update can also be triggered by a timer overflow event. In this update mode, the write operation to the DAC data register is held until the corresponding timer overflow event (Timer 3, Timer 4 or Timer 2, respectively) occurs, at which time the contents of DACxH:DACxL are copied to the DAC input latch, allowing the DAC data to change to a new value. [page]

In order to ensure the detector has high enough sensitivity and response speed, the system uses a high-speed microcontroller 89C56, whose maximum frequency can reach 1MHZ, and can respond 1us after the detection target changes. At the same time, the powerful computing performance of the microcontroller can store certain states that occurred before and predict the current state, making the detector intelligent.

3 89C56 High-Performance Microcontroller
The core processor of the system is MicroChip's high-speed microcontroller 89C56. The chip uses a high-speed, pipelined 8051-compatible CIP-51 core with 32 I/O pins; it integrates a variety of standard peripheral interfaces, PGA, analog multiplexers, DAC and ADC, etc., which can minimize the number of peripherals and the size of PCB circuit boards; it has a 64K-byte in-system programmable FLASH memory, which supports full-speed, non-intrusive in-system debugging. It has the following main features:

l High-speed, pipelined 8051-compatible CIP-51 core, up to 1MIPS;

Full-speed, non-intrusive in-system debug interface (on-chip);

lTrue 12-bit, 100 ksps 8-channel ADC with PGA and analog multiplexer;

l Two 12-bit DACs with programmable update timing;

l64K bytes of in-system programmable FLASH memory;

4352 (4096 + 256) bytes of on-chip RAM;

l External data memory interface with addressable 32K bytes address space;

lHardware-implemented SPI, SMBus/I2C and two UART serial interfaces;

l5 general-purpose 16-bit timers;

lProgrammable counter/timer array with 5 capture/compare modules;

l On-chip watchdog timer, VDD monitor and temperature sensor.

The 89C56 with on-chip VDD monitor, watchdog timer and clock oscillator is a true independent system-on-chip. All analog and digital peripherals can be configured to be enabled or disabled by user firmware. Each MCU can operate with a voltage of 2.7V to 3.6V within the industrial temperature range (-45℃ to +85℃). All port I/O, -RST and JTAG pins allow 5V input signal voltage.

The 89C56 has an integrated JTAG debugging circuit, and the on-chip FLASH memory has the ability to be reprogrammed in the system, which can be used for non-volatile data storage and allows the 8051 firmware to be updated on site. Based on these characteristics of the chip, the analyzer has added a JTAG interface circuit to the hardware design. In this way, the analyzer can be connected to the microcomputer through a dedicated JTAG adapter, and the 89C56 MCU can be debugged non-invasively (without occupying on-chip resources), at full speed, and in the system using the Cygnal integrated development environment. The debugging system supports observing and modifying memory and registers, and supports breakpoints, watchpoints, single steps, and run and stop commands. When using JTAG debugging, all analog and digital peripherals can operate with full functionality. In addition, the in-system programming capability of the JTAG interface and the on-chip FLASH memory can be used to easily implement firmware upgrades. The internal structure of the 89C56 is shown in Figure 2.

Figure 2: 89C56 internal structure

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4 Intelligent prediction module
In addition to real-time detection of the noise state of the system under test, the system can also predict whether there will be more and larger noise signals in the future based on the noise conditions encountered before. The prediction principle is that every time a larger noise signal is found, the high-speed microcontroller collects and processes these noise signals, and stores the amplitude and duration of the noise in the memory outside the microcontroller. Once a new noise signal is detected next time, the noise signal is first collected and sent to the microcontroller, and then the microcontroller compares the noise signal in the library according to the amplitude and duration of the noise, and sets a threshold. If the difference in comparison is less than the threshold, the closest historical noise data is found from all data less than the threshold, and the historical noise data is marked (recording the number of matches). At this time, the system believes that it is likely to encounter a noise signal that has appeared repeatedly before, so it sends an alarm message to the system and continues to monitor the newly arriving noise signal. According to the preset matching degree (threshold), the final judgment of whether the current noise signal is a real repeated noise can be made. If, after comparison, it is found that the difference between all the data in the library exceeds the threshold, the noise signal currently detected is considered to be a new noise signal and is stored in the external memory. If the external memory is full, find a data with the smallest mark and overwrite it (that is, the overwritten data is the noise signal with the smallest probability of recurrence, and such signals are not very helpful for noise prediction). After designing according to this strategy, the detection system can make certain predictions and alarm functions for the noise signal currently encountered, so that the overall designer can analyze and locate the cause and timing of the noise according to the detector, and provide effective reference information for the final elimination of the noise signal. The data format for storing noise information is shown in Figure 3.

Figure 3: Data format for storing noise information

5 Summary of Innovation Points
The innovation of this paper is to organically combine high-speed microcontrollers with devices such as A/D converters to develop an intelligent detection system suitable for precision voltage-stabilized power supplies. In addition to the function of sensitively detecting noise signals, the system can also make predictions and judgments based on historical noise signals to provide designers with early warning information. The design and implementation of this detector has a great auxiliary effect in providing designers with effective precision and pure voltage. In addition, the system can also be applied to some other voltage detection environments.