Design of a simple digital clock based on FPGA using VHDL language

As a newbie, I am willing to share some of the little things I made. I remember it was a few days less than a year ago. Looking at the records, it was May 19, 2009.

The scene where I used the 51 single-chip microcomputer to make a digital clock. At that time, I used assembly language and was very anxious. I worked on it for three days and even asked the teacher for help.

Well, now we are using C, and the focus is on AVR.

But when I think about it, I still learned a lot this year, so at least I didn’t waste this year.

FPGA is quite interesting, but I don’t have time to study it because I’m busy with competitions.

However, I have survived until now by going to the library every night to learn the basics of VHDL and microcontrollers during my internship in the first two weeks of the semester.

I'm just going to brag a little bit. Today, my teacher told me that I can be his teaching assistant. I was really excited.

In fact, I have always felt guilty because I have no time to do it. It would be embarrassing if I couldn’t answer a difficult question one day.

I spent about 6 hours this afternoon making a digital clock.

VHDL (Very high speed integrated circuit Hardware Description Language) is an ultra-high speed integrated circuit hardware description language.

As the name suggests, since it is a hardware description, it is of course describing hardware. This language is equivalent to melting a digital circuit in the FPGA or CPLD chip.

The hardware FPGA chip is the EP2C35F672C6 of the Cyclone II series from ALTERA

The development board used is ALTERA, model DE2, and the software is Quartus II 8.0, which is the development software created by ALTERA for its own products.

It is said to be 5000 RMB, and because it is for school teaching, it costs 2500 RMB if bought in bulk (but when I looked at it, only the chip is expensive, I think they made at least 1000 RMB from this board). I originally thought that the teacher would not lend it to me, but he didn’t seem to mind, and he took the initiative to lend it to me, uh…

No more words, just post the program

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fpq is
port(clk : in std_logic;
  k : in std_logic;
  k1 : in std_logic;
  k2 : in std_logic;
  ge : out std_logic_vector(0 to 6);
  shi : out std_logic_vector(0 to 6);
  feng : out std_logic_vector(0 to 6);
  fens : out std_logic_vector(0 to 6);
  shig : out std_logic_vector(0 to 6);
  shis : out std_logic_vector(0 to 6));
end fpq;

architecture first of fpq is
 signal clock : integer range 0 to 24999999;
 signal ge_t : integer range 0 to 9;
 signal shi_t : integer range 0 to 5;
 signal feng_t : integer range 0 to 9;
 signal fens_t : integer range 0 to 5;
 signal shig_t : integer range 0 to 9;
 signal shis_t : integer range 0 to 2;
 signal temp : integer range 0 to 9;
 
begin
t0: process(clk)
 begin
  if (clk'event and clk='1') then
   clock <= clock + 1;    
   if clock = 24999999 then
---------------------------------------------
   if k='0' then
---------------------------------------------
   
       if ge_t = 9 then
     ge_t <= 0;
     if shi_t = 5 and ge_t = 9 then
      shi_t <= 0;
      if feng_t = 9 and shi_t = 5 then
       feng_t <= 0;
       if fens_t = 5 and feng_t = 9 then
        fens_t <= 0;
        if shis_t = 2 and shig_t = 3 and fens_t = 5 then
         shig_t <= 0;
         if shis_t = 2 and shig_t = 3 then
          shis_t <= 0;
         else
          shis_t <= shis_t + 1;
         end if;
        else 
         if shig_t = 9 and fens_t = 5 then
          shig_t <= 0;
         else
          shig_t <= shig_t +1;
         end if;
        end if;
       else
        fens_t <= fens_t + 1;
       end if;
      else 
       feng_t <= feng_t + 1;
      end if;
     else
      shi_t <= shi_t + 1;
     end if;
    else
     ge_t <= ge_t + 1;
    end if;   
  else
   if k1='0' then
    if feng_t = 9 then
     feng_t <= 0;
     if fens_t = 5 then
      fens_t <= 0;
     else
      fens_t <= fens_t + 1;
      end if; 
    else
     feng_t <= feng_t + 1;
    end if;        
   end if;
   if k2='0' then
    if shig_t = 3 and shis_t = 2 then
     shig_t <= 0;
     shis_t <= 0;
    else     
     if shig_t = 9 then
      shig_t <= 0;
      if shis_t = 2 then
       shis_t <= 0;
      else
       shis_t <= shis_t + 1;
      end if;
     else
      shig_t <= shig_t + 1;
     end if;
    end if;        
   end if;
  end if; 
------------------------------------------------   
  end if;
 end if; 
------------------------------------------------  
 end process t0;
 
c:  process(clk,ge_t,shi_t,feng_t,fens_t,shig_t,shis_t) 
 begin
  case ge_t is
  when 9 => ge <= "0000100";
  when 8 => ge <= "0000000";
  when 7 => ge <= "0001111";
  when 6 => ge <= "0100000";
  when 5 => ge <= "0100100";
  when 4 => ge <= "1001100";
  when 3 => ge <= "0000110";
  when 2 => ge <= "0010010";
  when 1 => ge <= "1001111";
  when 0 => ge <= "0000001";
  end case;
  
  case shi_t is
  when 5 => shi <= "0100100";
  when 4 => shi <= "1001100";
  when 3 => shi <= "0000110";
  when 2 => shi <= "0010010";
  when 1 => shi <= "1001111";
  when 0 => shi <= "0000001";
  end case;
  
  case feng_t is
  when 9 => feng <= "0000100";
  when 8 => feng <= "0000000";
  when 7 => feng <= "0001111";
  when 6 => feng <= "0100000";
  when 5 => feng <= "0100100";
  when 4 => feng <= "1001100";
  when 3 => feng <= "0000110";
  when 2 => feng <= "0010010";
  when 1 => feng <= "1001111";
  when 0 => feng <= "0000001";
  end case;
  
  case fens_t is
  when 5 => fens <= "0100100";
  when 4 => fens <= "1001100";
  when 3 => fens <= "0000110";
  when 2 => fens <= "0010010";
  when 1 => fens <= "1001111";
  when 0 => fens <= "0000001";
  end case;
  
  case shig_t is
  when 9 => shig <= "0000100";
  when 8 => shig <= "0000000";
  when 7 => shig <= "0001111";
  when 6 => shig <= "0100000";
  when 5 => shig <= "0100100";
  when 4 => shig <= "1001100";
  when 3 => shig <= "0000110";
  when 2 => shig <= "0010010";
  when 1 => shig <= "1001111";
  when 0 => shig <= "0000001";
  end case;
  
  case shis_t is
  when 2 => shis <= "0010010";
  when 1 => shis <= "1001111";
  when 0 => shis <= "0000001";
  end case;
 end process c;
end first;

It is similar to assembly language, haha. Since I am a newbie, many of my programs are based on the idea of ​​single-chip microcomputer. In fact, VHDL and C, FPGA and single-chip microcomputer are two different languages ​​and chips. The main thing is to have the concept of parallel thinking and state machine. Unfortunately, I don't seem to have any of them now.

The setting mode switch is sw01., the minute setting buttons are key01, key02.

Video address: http://v.youku.com/v_show/id_XMTcxMTMzODYw.html But it’s very blurry. Tragic.