Design and Implementation of Digital Frequency Synthesizer Based on FPGA

A digital frequency synthesizer (DDS) is a digitally controlled phase-locked frequency multiplier. Its output frequency is an integer multiple of the reference frequency. The frequency selection switch changes the frequency division ratio to control the output signal frequency of the voltage-controlled oscillator. Compared with traditional frequency synthesizers, DDS has the advantages of low cost, low power consumption, high resolution and fast conversion time. It is a key technology for realizing full digitalization of equipment and is widely used in the fields of communications and electronic instruments.

1 Basic Principles of DDS
The working principle of DDS is to generate a sine wave with controllable frequency and phase in the form of a digitally controlled oscillator. The circuit generally includes a reference clock, a frequency accumulator, a phase accumulator, an amplitude/phase conversion circuit, a D/A converter and an LPF (Low Phase Filter).

The specific working process of DDS is shown in Figure 1. The N-bit phase accumulator consists of an N-bit adder and an N-bit accumulator register. For each clock pulse, the N-bit adder adds the frequency control word K and the accumulated phase data output by the N-bit accumulator register, and sends the result of the addition to the input end of the accumulator register. On the one hand, the accumulator register feeds back the new phase data generated after the previous clock cycle to the input end of the adder, so that the adder continues to add the frequency control word K under the action of the next clock; on the other hand, this value is used as a sampling address and sent to the amplitude/phase conversion circuit to output the corresponding waveform data. Finally, the waveform data is converted into the required analog waveform by the D/A converter and LPF.
Under the action of the reference clock, the phase accumulator performs linear phase accumulation. When the N-bit phase accumulator accumulates IV times, an overflow will occur, thus completing a cycle, which is also the frequency cycle of the DDS signal.
The output frequency fout of the DDS module is a function of the system operating frequency fclk, the number of bits of the phase accumulator N and the frequency control word K. The mathematical relationship is given by equation (1):

Its frequency division ratio is K/2N.

2 System Design
2.1 Design of Phase Accumulator
The phase accumulator is a typical feedback circuit, which is composed of an N-bit full adder and an N-bit accumulation register cascaded together to perform accumulation operations on binary codes representing frequencies. The number of bits of the phase accumulator N=32. A higher frequency resolution can be achieved. The module is written in Verilog language. The simulation circuit is shown in Figure 2.

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2.2 Design of ROM for storing waveform signals
The design of the ROM of this module is based on the open IP core of ALTERA, which is automatically generated. The stored sine wave waveform file, that is, the initialization file, is written in C language to generate waveform data and store it in ROM. Since the DAC device used is 8-bit input, the ROM data width designed in this paper is 8, but in order to improve the accuracy, the memory depth is selected as 1024. The simulation circuit is shown in Figure 3.

2.3 System overall module and simulation diagram
The overall circuit diagram of this system is shown in Figure 4, which consists of three parts: accumulator, 32-bit register, and ROM for storing waveforms. The accumulator performs DDS phase adjustment, and the output result is sent to the 32-bit D flip-flop to generate the address signal for reading ROM. Due to the limitation of ROM, we intercept the upper 10 bits as the address signal for reading ROM to generate a stable signal. The subsequent ADC and filter circuit are input for processing and output a stable waveform. The simulation circuit is shown in Figure 5. The system has well realized the reading of waveform data.

3 Conclusion
Based on the working principle of DDS, this paper designs and implements DDS direct frequency synthesis in VerilogHDL language on the FPGA development platform. After D/A conversion and external filtering and shaping circuit processing of waveform data, the output frequency-adjustable sine wave can be used as a signal source. It has good practical value.