Meeting the needs of DC/DC converters for FPGA power design

Electronic systems that require extensive digital processing are often implemented using field-programmable devices such as FPGAs or CPLDs rather than custom application-specific integrated circuits (ASICs). Although custom ASICs may have cost advantages over field-programmable devices, field-programmable devices offer advantages such as instant manufacturing turnaround, low startup costs, and design speed and ease. These advantages have made FPGAs and CPLDs the devices of choice for implementing complex digital systems such as Ethernet switches and routers, storage area network equipment, and multimedia content delivery systems.

The process of designing a circuit using an FPGA or CPLD consists of the following general steps: design entry, design verification, design compilation, and device programming. The design entry phase consists of capturing the design, either by creating a graphical schematic using a computer-aided design tool or by describing the circuit using a hardware description language such as Verilog or VHDL. After the design is captured, it is verified by using circuit simulation to check for correct functionality and performance. If the circuit does not meet the required performance, the engineer returns to the design entry phase to adjust the design and then repeat the design verification phase. The design entry and design verification steps may be repeated several times before the design meets all functional and performance requirements. After obtaining a satisfactory design, the engineer "assembles" the design using software provided by the FPGA or CPLD device vendor to configure the device that implements the design. The compiled file is downloaded to the FPGA or CPLD and the internal logic device is programmed to have the correct functionality.

Powering Field Programmable Devices

There are three basic power rails that are typically used to power an FPGA: the core rail, the I/O rail, and the auxiliary rail. Each of these rails has different load power requirements. The core rail, VCCINT, supplies power to the device's internal logic and typically has the most stringent current requirements. For previous generations of FPGAs, the voltage on VCCINT could be as high as 3.3V, while current devices can go as low as 1.2V. The I/O rail, VCCIO, supplies power to the FPGA's input/output blocks. The voltage on this rail can be 1.5V, 1.8V, 2.5V, or 3.3V, depending on the I/O standard being used. The specific I/O standard you choose is influenced by the device the FPGA will be communicating with. The auxiliary rail, VCCAUX, is used to power the digital clock manager and JTAG I/O on the FPGA and is typically 2.5V or 3.3V.

Variable power requirements

By repeating the above design compilation and downloading steps, engineers can change the programming and configuration of FPGA or CPLD at any time. There is no limit to the number of times the FPGA can be reconfigured according to the requirements of the new design. There is no need to change the traces on the circuit board, replace components, or re-solder, so faults can be solved and adjustments can be made very quickly and conveniently. In addition, functions and features can be added to a given design without affecting the physical design. This gives field programmable devices a huge advantage as a means of implementing complex digital systems.

However, this flexibility comes at a price. The power requirements of an FPGA, specifically the supply current it consumes, are proportional to the complexity of the design. Reconfiguring an FPGA to perform new functions will change the requirements of the power system that powers it. The more an FPGA is used, the more current it will require. Current requirements also increase with clock frequency, so the faster the FPGA, the more power it consumes. Therefore, changes in the FPGA's functionality will dictate changes in the power design.

Monolithic Dual-Channel Buck Converter

To meet the demand for compact and flexible power systems and to provide digital designers with a solution that can quickly design and reconfigure FPGA power, Intersil has introduced the ISL*26. The ISL*26 is a monolithic synchronous step-down converter with dual outputs that can provide up to 6A of total load current with up to 95% efficiency. The two output voltages are logic-adjustable or resistor-adjustable, and the user can configure the load current for each output channel. Therefore, if the FPGA/CPLD power requirements change during the design process, the new requirements can be met by simply re-specifying the load current for each channel.

This fully integrated synchronous step-down DC/DC converter eliminates the engineering work of selecting power MOSFETs, determining loop compensation parameters, and simplifies the inductor and capacitor selection process. The overall component count is reduced because the internal high-side MOSFET is implemented with a PMOS device instead of a typical NMOS device, eliminating the need for a bootstrap capacitor. The internal digital soft-start capability and internal loop compensation eliminate the external soft-start capacitor and external RC compensation network. The thermally enhanced QFN package, high operating frequency of 1.1MHz, and reduced BOM component count enable a compact power solution for the FPGA and VCCINT and VCCIO rails (Figure 1).

Figure 1: Functional structure diagram of ISL*26

Configurable load current capability

ISL*26 uses a unique architecture consisting of user-configurable power modules to facilitate rapid design of power systems. The power module architecture allows partitioning of six 1A modules with four power configuration options. Each synchronous converter channel is matched with a master power module. The remaining four power modules are slave modules that the user can assign to any of the master converter channels, as shown in Figure 2.

Figure 2: ISL*26 power module architecture

With these power modules, the load current capability of each channel of ISL*26 can be specified. The chip contains two logic pins, ISET1 and ISET2, to arrange the load current distribution for each channel according to the following table:

Each power module has its own power connection, PVIN, and inductor connection, LX. The ISL*26 can be used to regulate the output voltage from one or two input supplies. As the load current requirements of a given power design change, the design can be re-adjusted with minimal effort. Because the ISL*26 contains internal power switches and is internally compensated, changes in load current sharing between channels can be achieved by changing the logic levels of ISET1 and ISET2, as well as the PVIN and LX connections to the chip. Figures 3 and 4 show some typical configurations.

Figure 3: ISL*26 in a single-supply 3A/3A output current configuration

Figure 4: ISL*26 in a single-supply 4A/2A output current configuration

Flexible output voltage selection

The ISL*26 is capable of programming the output voltage of each channel without the use of external feedback resistors. Four logic pins, V1SET1, V1SET2, V2SET1, and V2SET2, select the output voltage for each channel from a common list of values. Essentially a 2-bit VID input, further facilitates redesign and retargeting because it allows the output voltage to be adjusted through logic rather than by making physical changes to the power board and its components, allowing changes to be implemented quickly and reliably. In addition, this 2-bit VID input allows digital control of the output voltage of the ISL*26 converter channels in those systems where such control is required. Table 1 lists the output voltage selections.

Table 1: Output current configuration

Table 2: Output voltage configuration

Eliminating the need for feedback resistors simplifies the design, reduces component count, and improves overall system accuracy. This convenience in output voltage selection does not sacrifice design flexibility, however, as the ISL*26 retains the traditional resistor divider method of setting the output voltage. The chip's internal reference voltage is 0.6V, and the output voltage of each channel can be set to any value between 0.6 and 4V using resistor feedback when using a 5V output supply.

Integrated fault protection

The ISL*26 features overvoltage, undervoltage, overcurrent, and overtemperature protection mechanisms so that all fault monitoring and protection functions are fully integrated into one chip and no external components are required. In an overvoltage condition (output voltage is above the overvoltage level - 115% of the reference voltage), the ISL*26 will actively try to regulate the output voltage down to the specified value. In the undervoltage protection condition, the feedback voltage is monitored and compared to the undervoltage level (85% of the reference voltage). If an undervoltage condition is detected on one converter channel, a 4-bit counter is incremented once. If an undervoltage condition is detected on both converter channels in the same switching cycle, the 4-bit counter is incremented twice. This counter continues to increment each time an undervoltage condition is detected on a converter channel. Once the counter overflows, the undervoltage protection logic shuts down both converters.

The overcurrent protection circuit also uses a 4-bit counter to record overcurrent events. The current in each power module is measured and compared to the overcurrent level appropriate for the specific power module configuration used. If the measured current exceeds the overcurrent threshold, a 4-bit up/down counter is incremented by 1. If the measured current drops below the overcurrent threshold before the counter overflows, the counter is reset. If both converter channels experience an overcurrent condition in the same switching cycle, the counter is incremented by 2. Once the counter overflows, both converter channels are cut off. If the current measured in both converter channels drops below the overcurrent level in the same cycle, the counter is reset.

Finally, for over-temperature protection, an internal temperature sensor continuously monitors the junction temperature of the ISL*26. If the temperature exceeds 150°C, the sensor commands the ISL*26 to shut down both sensor channels and latch off.

Voltage Monitoring and Power Sequencing

Each converter channel of the ISL*26 has its own enable signal and power-good signal. This allows for individual control and monitoring of each output voltage, making voltage tracking and power sequencing possible. There are two enable signals, EN1 and EN2, used to enable or disable each channel. There is also a system enable signal, EN, which can be used to start or shut down both channels simultaneously. When the enable signal is received and the channel is enabled, a digital soft-start function increases the output voltage by gradually increasing the reference voltage at fixed intervals of 20ms. For voltage monitoring, each converter channel has its own power-good signal, which can be determined when the output voltage of a channel exceeds the regulation limit. Sequencing the two output voltages of the ISL*26 is achieved by connecting the power-good signal of one channel to the enable input of the other channel. In this configuration, the second output will not start the soft-start cycle when the first output is in regulation, as shown in Figure 5.

Figure 5: Power sequencing control for ISL*26

Complete FPGA Power Solution

The ISL*26 represents a complete and environmentally friendly power supply solution due to its convenient configuration, integrated power devices, high efficiency, integrated fault monitoring and protection, support for the use of ceramic capacitors and RoHS compliance. Design changes can be implemented quickly, easily and reliably during the overall FPGA or CPLD system implementation, thus shortening the design cycle and reducing design iterations.