Design of Fiber Channel Interface Adapter Using Host Computer and FPGA Development Board

With the rapid development of storage technology, storage capacity has grown rapidly, and the data transmission speed of storage systems has become a major bottleneck. Fiber optic transmission has its speed advantage, however, fiber optic transmission is limited by the fiber channel interface. Therefore, a key technical issue in the application of fiber channel in high-speed data transmission is the interface design problem. This article has practical significance for effectively solving the bottleneck of high data transmission at the interface.

1 Solution Design

The complete implementation includes PC software programming and the underlying link implementation of the Virtex-5 development board. The PC software programming mainly implements link creation and deregistration control, data framing, data transmission control, and display during transmission; the VirteX-5 development board mainly implements data link penetration and supports the transmission process of the frame structure defined by the host computer.

As shown in Figure 1, the interface adapter function implementation process mainly includes the correct understanding of the protocol, the organization of the protocol frame structure and data structure, the design and writing of specific implementation modules, and the realization of the fiber optic communication interface adapter function in combination with the connection of the VirteX-5 underlying link.

2 Specific implementation of the design

2.1 Analysis and tailoring of the protocol

The FC protocol should be tailored appropriately for different application environments, and the protocol standard should be used as effectively as possible. The FC protocol is a five-layer protocol system, including: FC-0 layer, FC-1 layer, FC-2 layer, FC-3 layer, and FC-4 layer.

The functions of each layer are:

(1): FC-O: Mainly specifies the physical interface, including transmission media, transceivers and interfaces.

(2) FC-1: 8 B/10 B encoding; deserialization; bit and word synchronization.

(3) FC-2 specifies the transmission mechanism of Fibre Channel:

Detection and identification of ordered sets; FC port state machine; sending and receiving frames, and validity check when receiving frames; flow control; frame management; switching and sequence management; data frames and responses; multicast and broadcast; segmentation and reassembly; error detection and response.

(4)FC-3: Basic link service; Extended link service; Query group.

(5) FC-4: Mapping the upper layer protocol. This article mainly maps the MILstd-1553B protocol.

2.2 Design of the code for each module in software programming

The design part of software implementation: GUI module design, device abstraction layer design, task processing module design, FC protocol and physical function module design.

(1) The GUI part is mainly used for display, and can set the relevant parameters of the interface adapter and display the interface. The GUI module design content includes: overall interface, link parameter area, link establishment area, and information display area.

(2) Design of the device abstraction layer. This part is to shield the differences between different physical devices in the lower layer and provide a simpler way for the upper layer module to communicate with the logic. This layer needs to provide the device operation interface supported by the upper layer and the functional interface provided by the WinDriver driver by encapsulating it internally to achieve functional support for the upper layer.

(3) Design of the task processing module. It mainly implements different task operations for links and data. The link data area and the file data area need to save their respective task data and status. In addition, it is the basis for the GUI module to change the LIST, so it is also necessary to save the status and data of the lower layer protocol.

(4) Design of FC protocol and physical function module. This section mainly describes the task sending protocol and link establishment protocol. [page]

① Registration process for link establishment: Before data transmission, a link between the sender and the receiver needs to be established through registration. First, the sender embeds the address ID and other information to be registered into the frame information and sends the frame information to the receiver. Then, after receiving the frame information, the receiver interprets the relevant information. If it meets the frame integrity check, the two ends establish a link. If it does not meet the relevant check,

If the error is found, the registration process will be terminated.

② Link deregistration process: When a link needs to be deregistered, first, the sender embeds the address ID and other information to be deregistered into the frame information and sends the frame information to the receiver. Then, after receiving the frame information, the receiver interprets the relevant information. If it meets the frame integrity and other checks, both ends deregister the link. If it does not meet the relevant checks, the deregistration process is terminated.

③Data transmission process: Data transmission is the fundamental purpose of link establishment. The simplified data transmission process is shown in Figure 2.

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2.3 Virtex-5 Development Board's Bottom-Line Guarantee

(1) The system construction logic design mainly completes the following functions:

Control the PCIE hard core to interact with the upper-layer software; add CRC check to the upper-layer transmission data; complete the FC link initialization process; complete the FC flow control function; complete FC-2 error handling; control ROCKET I/O to send the upper-layer software data through ROCKET I/O; control ROCKET and I/O to transmit the received and recovered data to the upper-layer software.

(2) Module composition of logic design: The underlying logic control module mainly completes the FC physical layer communication. It mainly includes three parts: the sending module, the receiving module and the PCIE control module. Each module is divided into multiple sub-modules according to different functions. In the PCIE control module, there are some caches to store the data transmitted by the receiving module and the corresponding data information. The sending module also reads data from the cache of the PCIE control module and transmits it. Its principle block diagram is shown in Figure 3.

Data transmission module This module sends different information by reading the status information of the host computer. When ACK is enabled, the module sends ACK. When data is enabled, the module sends data with a fixed number of frames. The data sent is read from the cache, and CRC is added by the module. When idle, it sends IDLE code.

The data receiving module includes a receiving control module, a CRC module and a temporary buffer module. It mainly completes the reception of data and link control frames and preparation signals, and implements CRC verification. It determines different types of data frames or control frames based on the frame header and stores them in the buffer, and also stores the relevant information of the frame in the corresponding buffer.

PCIE interface control module This module mainly decodes the value of the register corresponding to the address on the PCIE bus into the corresponding enable, writes the data on the PCIE bus into the corresponding data sending buf-f, and ACK sends buff. Conversely, according to the enable of the logic input, it is decoded into the value of the corresponding register of the corresponding address on the corresponding PCIE bus, and writes the data receiving buffACK receiving buff data to the corresponding PCIE address.

2.4 Final Implementation

By combining the host computer with the FPGA development board, the high speed of the Fibre Channel interface adapter is achieved. The transmission effect diagram is shown in Figure 4.

3 Conclusion

Through the combination of the host computer and the FPGA development board, the design of the interface of the fiber channel in the high-speed data transmission process is simulated and realized. Although the design is realized in the form of a host computer and FPGA, it has certain reference significance for the actual development of the fiber channel interface adapter in terms of design ideas.