Serial FLASH SSF1101 in microcontroller

1 Overview

For single-chip data acquisition systems that work in the field or are inconvenient to communicate with the host computer, using a large-capacity, pluggable, easy-to-replace and carry smart card to store the collected data is a good data storage solution. SSF1101 is a 4Mbit serial interface programmable flash memory produced by Shanghai Xinmao Semiconductor Co., Ltd. The device uses SPI serial port mode to communicate with the single-chip or microcomputer without any peripheral components. Using the IC card packaging provided by the device, it can be very convenient to interface with the single-chip system to form a large-capacity data storage device. At the same time, the chip has the advantages of small package size, high integration, low voltage, large storage capacity, simple interface mode, etc., and has broad application prospects in the commercial and industrial fields.

2. Performance characteristics

SSF1101 is a 4Mbit serial FLASH memory with 4 device identification pins. It can be expanded to 16 pieces in a system at most, and its total storage capacity can reach 8M bytes. The performance characteristics of this device are as follows:

●SPI serial data interface complies with SPI standard;

●The device has 4M Bit flash memory, 512 pages, 1024 bytes per page;

●Built-in 4-bit device address decoding circuit, can directly connect in parallel to expand storage capacity, up to 16 pieces can be connected;

●With dual 1k-byte data buffers, data can be written or read during programming, and the read/write address is automatically incremented;

●High-speed page programming, typical time is 20ms;

●The typical time for high-speed page to data buffer transfer is 100 μs ;

●The typical time for page erase is 10ms;

●The typical device erase time is 2s;

●Built-in erase/program timing logic;

●Hardware write protection is available;

●The clock frequency is up to 10MHz;

●It works with a single 5V power supply, and low voltage 2.7~3.5V is available;

●Low power consumption, typical sleep current is 18 μA ;

●Compatible with CMOS level and TTL input/output level;

● Wide operating temperature range (commercial use);

●Built-in power-on reset circuit;

●When transferring or comparing between the data buffer and the main Flash, the unused data buffer and status register can be operated.

SSF1101 adopts two forms: 32-pin TSOP package and IC card package. Its TSOP package shape and pin arrangement are shown in Figure 1 (a), and the contact configuration of the IC card is shown in Figure 1 (b). The pin function description of the device is listed in Table 1.

Table 1 SSF110 pin description

3. Working Principle

SSF1101 has 4194304 bits of main storage unit, divided into 512 pages, 1024 bytes per page. In addition, SSF1101 also contains 2 SRAM buffers, each buffer has 1024 bytes, when a page in the main memory is being programmed, the buffer can still receive input data. SSF1101 uses SPI serial port to access its data, so the hardware design is very convenient, the system reliability is very strong, and the switching noise can be minimized. The chip does not require high voltage during programming, and the programming voltage is still the power supply voltage. Figure 2 shows the internal structure block diagram of SSF1101 memory.

SSF1101 accesses data through a simple SPI serial port. The operation of the device is controlled by the instructions issued by the host. A valid instruction includes a 4-bit operation code in one byte, a 4-bit device address, and the destination buffer or main storage address location. When CS is 0, the host sends a clock signal to the SCK end of the device to guide the operation code and address to be written from the SI end to the device. All instruction addresses and data are sent high first. The operation commands of SSF1101 are listed in Table 2. X in the table can take any value and it has no effect on the operation of the device.

Table 2 SSF1101 operation command table

3.1 Status Register (SR)

The SSF1101 has an 8-bit status register that can be used to indicate the working status of the device. The contents of this register can be read out through the "status register read" command. The register contents and definitions are as follows:

BF: Busy flag, when it is 1, it means the device is busy and cannot execute the operation command to the flash memory;

CF: comparison flag, when it is 1, it means that the content in the buffer is inconsistent with the specified flash memory page being compared;

WPF: Write protection flag, 1 means the device is in hardware write protection state;

Bit2~Bit0: capacity indication bit, all 1s indicate that the flash memory capacity is 4Mbit;

Res: reserved bit, temporarily set to 01;

When the device is correctly powered on and reset, SR is 00001111B.

3.2 Command Operation Instructions

(1) Buffer transfer

There are three types of buffer transfer. First, the content of the specified flash memory page can be copied to buffer 1 or buffer 2 through the flash to buffer transfer command. The command code for transferring to buffer 1 is: 1100ddddd PA11-PA0 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX, a total of 32 bits, and continue to keep SCK to at least the 35th cycle. PA11-PA0 are the flash memory pages specified to be transferred. If they exceed the range of the device, they are automatically modulo. When CS is set high, the transfer operation starts, and the BF bit in the status register is valid. It takes about 100 μs to complete the transfer operation . After completion, the BF flag is cleared (in the following commands, if not specifically stated, the meaning of the command code and the operation timing are the same. In addition, the operation for buffer 2 is only different in the command, and the rest is exactly the same. The following commands are the same).

When sending commands from the buffer to the flash memory using the built-in erase cycle, the built-in erase cycle is generally used to erase the specified flash page first, and then the contents of the buffer are copied to the specified flash page.

When sending commands from the buffer to the flash memory without using the built-in erase cycle, the contents of the buffer can be directly copied to the specified flash memory page.

(2) Read and write buffer

The read buffer command is used to read one or more bytes of data in buffer 1 (or 2). The command code is:

1110dddddXXXXXXXXXBA11-BA0.

Among them, BA11-BA0 are used to specify the starting address of data read from the buffer. If the buffer size is exceeded, the modulus is automatically taken. The device starts to output data from the SO pin at the falling edge of the 35th SCK, with the high bit first. After reading a byte, the buffer address is automatically increased by 1, and then the data of the next address is output. If the end of the buffer is reached, it automatically returns to the starting address of the buffer. An additional 3 to 7 pulses are required after the last byte is output.

The write buffer command is used to write one or more bytes of data into buffer 1 (or 2). The command code is:

0110dddddXXXXXXXXXBA11-BA0

Among them, BA11-BA0 are used to specify the start address of the write buffer. If the address exceeds the buffer size, it will automatically take the modulus. The device starts to receive data from the SI pin (high bit first) at the rising edge of the 33rd SCK, writes to the buffer after receiving a byte, and automatically adds 1 to the buffer address and continues to receive data from the next address. If it reaches the end of the buffer page, it will automatically return to the start address of the buffer. An additional 3 to 7 pulses are required after the last byte is output.

(3) Flash memory direct read

The flash direct read command is used to read data directly from the flash page without passing through the buffer and without affecting the content in the buffer. The command code is:

0001ddddd PA11-PA0 BA11-BA0.

Among them, PA11-PA0 are used to specify the flash memory page to be operated. If it exceeds the range of the device, it will automatically take the modulus; BA11-BA0 are used to specify the starting address of reading data from the page. Similarly, if it exceeds the page size, it will automatically take the modulus. The device starts to output data from the SO pin at the falling edge of the 35th SCK, with the high bit first. After outputting a byte, the data address in the page is automatically increased by 1, and then the data of the next address is output. If the end of the page is reached, it will automatically return to the beginning of the page.

(4) Comparing flash pages and buffers

This command is used to compare the data in the specified flash page and the buffer to see if they are the same. The comparison starts after being set high, and BF is set to 1. If the comparison result is different, the CF bit of the status register is set to 1, otherwise CF is cleared, and BF is cleared after the comparison is completed.

(5) Read status register

The status register read command is used to read the value of the status register in the device.

(6) Chip Erase

The chip erase command is used to erase the data of all pages of the flash memory. One erase cycle takes about 2s.

4 Specific applications

Since SSF1101 has a large storage capacity of 512 kbytes, it can be widely used in digital voice storage, image storage, data storage and other application fields to form a large-capacity single-chip data acquisition system. The IC card reading and writing circuit composed of AT89C52 single-chip microcomputer and SSF1101 is shown in Figure 3.

In Figure 3, P1.0, P1.1, and P1.2 of AT89C52 are connected to the interfaces SI, SCK, and SO of SSF1101 SPI respectively to realize simple three-wire serial communication. P1.3 is connected to CS to control access to the device. C9 and C10 in the figure are the on switches of the IC card holder. When the IC card is inserted, the switch is closed, and the C1 terminal is connected to the +5V power supply. After the SSF1101 is powered on and reset, the read-write circuit enters the normal read-write state. When the IC card is pulled out, the C1 terminal sends an interrupt request to the INT0 terminal of AT89C52 through the resistor R2, thereby turning to the card drop interrupt processing program. The following program code is the read-write IC card program that matches the above hardware circuit:

; Bit definition

SI BIT P1.0; serial data input

SCK BIT P1.1; serial clock

SO BIT P1.2; serial data output

CS BIT P1.3; Chip select control

;Memory definition

RCMD ＥＱＵ ３０Ｈ; card reading command unit

PAH EQU 31H; Flash memory page high unit

PAL EQU 32H; Flash memory page low unit

BAH EQU 33H; Flash memory address high unit

BAL EQU 24H; Flash memory address low unit

IＣＲＤＡＴＡ ＥＱＵ ２０Ｈ; read and write data buffer address

NUMBER EQU 80H; data block length

; Read IC card subroutine, using flash memory direct reading method

ＲＣＡＲＤ： ＳＥＴＢ

SETBB SI ; Initialize SPI

SET Ｂ ＳＯ

ＣＬＲ ＳＣＫ

MOV RCMD, #10H; "Flash memory direct read" command

MOV DAH, #00H; 00 page

ＭＯＶＤＡＬ，#00Ｈ

MOV BAH, #00H; 00 address

ＭＯＶＢＡＬ，#00Ｈ

CLR CS ; Select chip

MOV R0, #RCMD; points to the command unit

MOV R1, #04H; 4-byte command

T RCMD： ＭＯＶ A，＠Ｒ0

LCALL S OUT ;Call the sending subroutine

ＩＮＣＲ０

DJNZ R1,T RCMD

MOV R0, #ICRDATA; points to read and write data

Buffer first address

ＭＯＶＲ1，#ＮＵＭＢＥＲ

ＲＩＣＤＡＴＡ： ＬＣＡＬＬ ＳＩＮ ；Call receiving subroutine

MOV @R0, A; read 128 bytes of data to the host

ＩＮＣＲ０

DJNZ R1，RICDATA

SET CB CS

RET

; Write IC card subroutine; data is first written to the buffer, and then written to the main memory using the built-in erase cycle from buffer 1 to memory transfer command

WCARD: SETB CS

SETB SI

SET Ｂ ＳＯ

ＣＬＲ ＳＣＫ

MOV RCMD, #60H; "write buffer 1" command

MOV BAH, #00H; write 00H address

MOV BAL, #00H; unit

ＣＬＲ ＣＳ

ＭＯＶＲ0，#RCMD

ＭＯＶＲ1，#0４Ｈ

T RCMD1: MOV A,@R0

LCALL SU OUT

ＩＮＣＲ０

DJNZ R1,T RCMD

MOV R0, #ICRDATA; points to the read and write buffer

ＭＯＶＲ1，#ＮＵＭＢＥＲ

T RDATA： ＭＯＶ Ａ，＠Ｒ0

LCALL SU OUT

ＩＮＣＲ０

DJNZ R1, T-RDATA

SET SB SK

ＣＬＲ ＳＣＫ

SET SB SK

ＣＬＲ ＳＣＫ

SET SB SK

ＣＬＲ ＳＣＫ

ＭＯＶＲＣＭＤ，#0Ａ0Ｈ

ＭＯＶＤＡＨ，#00Ｈ

ＭＯＶ ＤＡ，#00Ｈ

ＣＬＲ ＣＳ

ＭＯＶＲ0，#RCMD

ＭＯＶＲ1，#0４Ｈ

T RCMD2: MOV A,@R0

LCALL SU OUT

ＩＮＣＲ０

DJNZ R1, T-RCMD

SET CB CS

LCALL DL30MS; delay 30ms

RET

; Receive one byte of data program

S-IN: MOV R6, #8

RSHIFT： ＭＯＶ Ｃ，ＳＯ

SET SB SK

RLC A

ＣＬＲ ＳＣＫ

DJNZ R6，RSHIFT

RET

; Send one byte of data subroutine

S OUT: MOV R7, #8

TSHIFT: RLC A

MOV SI, C

SET SB SK

NOP

ＣＬＲ ＳＣＫ

NOP

ＣＬＲ ＳＣＫ

DJNA R7，TSHIFT

RET

5 Conclusion

The serial IC card packaging form of the SSF1101 serial flash memory is very convenient for interfacing with a single-chip microcomputer to form a portable data storage device. At the same time, its large storage capacity can also meet the requirements of application systems with large data storage volumes. Therefore, this device has a broad application prospect in the field of data storage.