Samsung is reportedly entering panel-level packaging ahead of TSMC

On June 27, South Korean media Business Korea reported on June 24 that Samsung Electronics' semiconductor packaging industry has made significant progress and will lead TSMC in entering the panel-level packaging (PLP) field.

Kyung Kye-hyun, former head of Samsung Electronics' semiconductor (DS) division, attended a shareholders' meeting in March this year and elaborated on the necessity of promoting PLP technology.

He explained: “AI semiconductor chips (rectangular components with circuits) are typically 600mm x 600mm or 800mm x 800mm in size, so technologies such as PLP are required, which Samsung is currently actively developing and strengthening collaboration with customers.”

TSMC is working on a new advanced chip packaging method that uses rectangular substrates instead of traditional round wafers to place more chips on each wafer.

Sources revealed that rectangular substrates are currently being tested and are 510 mm x 515 mm in size, with more than three times the usable area of ​​round wafers. The use of a rectangular shape means that there will be less unused area left at the edges.

Nikkei Asia reported: "TSMC's research is still in the early stages and mass production is expected to take several years. Although TSMC was previously skeptical about using rectangular printed circuit boards, its entry into the research field means an important technological shift."

Market research firm IDC reported that if Nvidia wants to complete its AI semiconductor orders, it needs half of TSMC's CoWoS production capacity, but currently only about one-third of it can be implemented.

TSMC plans to more than double the process's capacity by the end of the year, however, competition for TSMC's CoWoS output from fabless companies such as AMD and Broadcom makes this goal challenging.