Cadence Dynamic Duo Verification Solution Accelerates Chip Development Cycle

Despite the 14+7 days of quarantine, Cadence Asia Pacific System Solutions Senior Director Zhang Yongzhuan made a special trip from Taiwan to the mainland, with one important purpose being to promote Cadence's latest Dynamic Duo verification solution to customers. The solution includes two products, the Palladium Z2 hardware simulation acceleration platform and the Protium X2 prototype verification system.

Cadence translated Dynamic Duo into system dynamic twin swords. Zhang Yongzhuan said that Cadence is implementing a new strategic thinking, which is to provide customers with one-stop solutions from the perspective of vertically integrated systems.

New Trends in Chip Design

Zhang Yongzhuan said that in Cadence's view, many new changes are taking place in the chip design industry.

First, the product design cycle is shortened.

Second, with the popularity of multi-core heterogeneous computing, the complexity of design and verification is increasing.

Third, it is the integration of new designs and derivative products.

Fourth, the status of system and software development is improving, and many system companies have now begun to determine the trends of chips and industries.

5. Develop in a collaborative way between software and hardware.

Sixth, the continuous development of IP has resulted in more than 80% of the work in SoC design being reusable.

7. 60% of the challenges come from software.

For these reasons, the idea of ​​design-left shift is becoming more and more popular in chip development projects, which requires detailed simulation of the chip before tape-out to ensure that it can meet the requirements in terms of function, power consumption, efficiency, etc. At the same time, prototype verification work also needs to be done as early as possible to better perform software debugging.

Zhang Yongzhuan said that since simulation and prototype verification have different requirements, simulation requires higher accuracy, visibility, sufficient capacity and scalability, while prototype verification requires higher speed. Therefore, Cadence also launched the Dynamic Duo system to meet different hardware acceleration needs.

Dynamic Duo's three major advantages

Zhang Yongzhuan cited the three major advantages of Dynamic Duo. The first is stronger performance. Palladium and Protium products have doubled the capacity and 50% performance compared to the previous generation. The Module compiler technology is used to split the design during the compilation process to ensure support for simulation acceleration of larger chips, so that the compilation of 10 billion gates SoC can be completed within 10 hours on the Palladium Z2 system, and fully supports large-scale processors including AI and data centers. At the same time, Palladium uses the processor developed by Cadence itself, avoiding the problem of FPGA P&R, so it has more powerful Debug capabilities. In addition, Trigger Condition is supported, and fast iteration and convergence can be achieved without recompiling during Debug modifications.

Second, the two products use the same compiler, which can reduce the compilation time cost of engineers.

It is the unification of the front end, including physical or virtual interfaces, such as PCI, USB, Ethernet, etc. Combined with a common compiler, this platform reuse method can achieve rapid migration and reuse.

"The platform approach can save the number of management personnel. A platform that used to require a group of people to be in charge of may now be managed by just one person," said Zhang Yongzhuan.

In order to better meet the company's verification project management needs, Cadence also has a verification management system, vManager, which allows the entire company's engineering team to know the verification progress, defects and manpower gaps, and use big data to assist in error location, thereby improving verification efficiency.

The platform is widely recognized by customers

According to data provided by Cadence, 9 of the top 10 supercomputer companies, 12 of the top 15 semiconductor companies, and 4 of the top 5 application processor companies have chosen Palladium Z1, and more than half of the companies have chosen Protium Z1.

The release of the Dynamic Duo platform has been highly praised by important customers and partners including NVIDIA, AMD, Arm, and Xilinx. Alex Star, Global Fellow and Methodology Architect at AMD, said, "One of the important achievements of AMD's success is to accelerate the chip development process and optimize AMD's left-shift strategy. Using Cadence Palladium Z2 and Protium X2 systems to improve performance can improve the throughput of pre-silicon workloads while ensuring functional consistency between hardware simulation and prototype verification. The ability to quickly start up and switch between Palladium Z2 hardware simulation and Protium X2 prototype verification in a short time provides us with the opportunity to optimize our own left-shift strategy when developing the most challenging SoC designs. By using servers with industry-leading third-generation AMD EPYC™ processors and Palladium Z2 and Protium X2 platform qualifications, customers will be able to bring industry-leading performance computing to the Palladium and Protium ecosystem."

Zhang Yongzhuan also revealed that among the domestic customers who currently choose hardware acceleration simulation platforms, nearly 95% of companies have chosen Cadence's Palladium.

"The Dynamic Duo platform is a key tool to enhance the company's competitiveness. It improves efficiency and accelerates product launch cycles, allowing the company to maintain its market leadership," Zhang Yongzhuan concluded.