TSMC is more than just a simple wafer foundry

Founded in 1987, TSMC has held its annual technology symposium since 1994, and this year marks its 25th anniversary (a point that was generally highlighted at the Santa Clara Convention Center). “The first Silicon Valley symposium had less than 100 attendees, and now we have more than 2,000 attendees,” said Dave Keller, president and CEO of TSMC North America.

Dr. Cheng-Ming Liu, Director of Corporate Development at TSMC, described the unique needs of TSMC’s automotive customers, especially the need for continuous supply over longer product lifecycles. He said:

“Our commitment to the ‘old’ processes is unwavering. We have never closed a plant or shut down a process technology.”

Dr. Y.-J. Mii, Senior Vice President of Research and Development/Technology Development, highlighted three eras of process technology development, as shown in the figure below:

In the first phase, Dennard Scaling refers to the miniaturization of FEOL linear lithography dimensions at a ratio of “s” (s < 1) in subsequent process nodes to achieve an increase in circuit density (1 / s^2) (measured in gates / mm^2). The focus of the next phase is on material improvements, while the focus of the current phase is on design-technology co-optimization (more on this soon).

Later in the webinar, Dr. Doug Yu, Vice President of Integrated Interconnect and Packaging R&D, described how advanced packaging technology has focused on scaling, albeit for a shorter period of time. “For more than a decade, packaging has also provided two-dimensional improvements in redistribution layer (RDL) and bump pitch lithography. With the multi-die, 3D vertical stacking packaging technology we describe today – especially TSMC’s SoIC products, we have achieved huge improvements in circuit density. S equals zero. Or in other words, we have achieved infinite scaling. (In fact, it is easy to foresee that product technology will start to be measured in gates/mm^3.)

A brief introduction to the current status of TSMC's advanced process technology

1. N7/N7+ (7nm/7nm+)

TSMC announced the N7 and N7+ process nodes at a seminar two years ago.

N7 is the “baseline” FinFET process, while N7+ provides better circuit density for selected FEOL layers by introducing EUV lithography technology. Design IP needs to be redeployed from N7 to N7+ to achieve a 1.2x improvement in logic gate density. Key highlights include:

• N7 is now in production, with more than 100 new tape-outs (NTOs) expected in 2019.

• Introduction to key IP: 112Gbps PAM4 SerDes.

• N7+ benefits from continued EUV output power (~280W) and uptime (~85%) improvements. TSMC said: "While we expect further improvements in power and uptime, these measures are sufficient to drive N7+ capacity growth."

• TSMC is focusing on reducing defect density (D0) at N7. According to TSMC, “After the initial yield increase, the D0 improvement ramp is faster than previous nodes.”

• TSMC showed a split in N7 die sizes: <100 mm^2 for mobile customers, >300 mm^2 for HPC customers.

• TSMC also said for the first time I know of that they are tracking D0 specifically for "large chips" and reported relatively reduced learnings for large designs compared to other N7 products.

• N7+ will ramp in the second half of 2009 and will demonstrate D0 defectivity comparable to N7.

2. Making 5G a reality

TSMC invited Qualcomm CTO Jim Thompson to give his thoughts on N7 - it was a very enlightening talk:

• “The N7 is an enabler of 5G, as demonstrated by our latest SnapDragon 855 release.”

• "5G MIMO with 256 antenna elements supports 64 simultaneous digital streams, or 16 users each receiving four data streams on a single phone."

• “Antenna design is really critical for 5G to overcome path loss and signal blockage. People are looking for new and innovative antenna implementations – at the end of the day it’s just math, although it’s certainly complex math.”

• “There are certainly many skeptics about the rate of 5G adoption. However, 5G delivers much faster speeds than 4G. In the rollout plan, only five operators and three OEM devices supported 4G, mostly in the U.S. and South Korea. Currently, there are more than 20 operators and more than 20 OEM devices focused on 5G deployment, including in Europe, China, Japan, and Southeast Asia.”

• “Also, don’t overlook the deployment of 5G in applications beyond consumer mobile phones, such as wireless factory automation. Communications with industrial robots require high bandwidth, low latency, and extremely high availability. Consider the opportunities that 5G brings for manufacturing flexibility in a wireless environment.”

3. N6 (6nm)

TSMC has launched a new node product, called N6. This node has some very unique characteristics:

Design rules compatible with N7 (e.g., 57 mm M1 pitch, same as N7)

N7-compatible IP models

EUV lithography for limited FEOL layers, "1 more EUV layer than N7+, leveraging learnings from N7+ and N5"

Stricter process control and faster cycle time than N7

Same EDA reference flow, filling algorithm, etc., as N7

N7 designs can simply be “re-taped out” (RTO) to N6 to improve EUV mask lithography yields

Alternatively, N7 designs can be submitted for new tape-out (NTO) by redeploying logic blocks using an N6 standard cell library (H240) that leverages “common PODE” (CPODE) devices between cells to increase logic block density by ~18%.

Risk production to begin in Q1 2020 (13-level metal interconnect stack shown)

Although the design rules are compatible with N7, N6 also introduces a very unique feature "M0 routing".

The figure below illustrates a “typical” FinFET device layout, where M0 is used only as a local interconnect to connect the source or drain nodes of the multi-fin device and is used within the cell to connect the common nFET and pFET schematic nodes.

I need to think more about the opportunities of using the M0 as a routing layer, TSMC has indicated that EDA router support for this feature is still qualified.

In my opinion, N6 is a continuation of TSMC’s roadmap to introduce a “half-node” process, as shown in the figure below.

The half-node process was both an engineering-driven and business-driven decision to provide a low-risk design migration path and a cost-reduction option for existing N7 designs as a “mid-life kicker.”

The introduction of N6 also highlights an issue that will become increasingly difficult. The migration of designs integrating external IP depends on the IP provider’s engineering and financial resources to develop, release (on a test site), characterize, and qualify the IP on the new node on an appropriate schedule. N6 provides an opportunity to introduce a kicker without being constrained by the release of external IP.

(IV) N5 (5nm)

Process node N5 incorporates additional EUV lithography to reduce the number of masks for layers that require extensive multi-patterning processing.

• Risk production started in March '19, high volume ramp up will be completed in Q2 2020 at Gigafab 18 in Tainan (Phase 1 equipment installation completed in March '19)

• Designed to support both mobile and high performance computing "platform" customers; high performance applications will want to use the new "ultra low Vt" (ELVT) devices

• 1.5V or 1.2VI/O device support

• Plans to offer N5P (“PLUS”) products that will provide +7% performance improvement at constant power, or approximately 15% power reduction over N5 at constant perf (one year after N5)

• N5 will use high mobility (Ge) device channels

Advanced Materials Engineering

In addition to the N5 high-mobility channel launch, TSMC also highlighted other materials and device engineering updates:

• Ultra-high density MIM product (N5) with 2X ff/um*2 and 2X insertion density

• New Low-K Dielectric Materials

• Metal reactive ion etching (RIE), replacing Cu damascene, achieving metal spacing <30um

• Graphene “cap” to reduce Cu interconnect resistivity

Improved local MIM capacitance will help address the increased current due to higher gate density. TSMC noted that high-performance (high switching activity) designs can achieve expected single-digit performance gains.

Both nodes 16FFC and 12FFC have received device engineering improvements:

• 16FFC+: +10% perf @ constant power, +20% POWER @ constant perf compared to 16FFC

• 12FFC+: +7% perf @ constant power, +15% POWER@ constant perf compared to 12FFC

NTOs for these nodes will be accepted in Q3 2019.

TSMC also briefly introduced its ongoing R&D activities for future node material research, e.g., Ge nanowire/nanoslab device channels, 2D semiconductor materials (ZrSe2, MoSe2), see the figure below (Source: TSMC).

Dr. JK Wang, Senior Vice President of Fab Operations, discussed in detail the ongoing efforts to reduce DPPM and maintain “manufacturing excellence.” Of particular note were the steps taken to meet the demanding reliability requirements of automotive customers. Highlights from Dr. Wang’s presentation included:

“Since the introduction of the N16 node, we have accelerated the rate of capacity ramp at each node in the first 6 months. N7 capacity will exceed 1 million 12-inch wafers per year in 2019. N10/N7 capacity has tripled since 2017 as Phases 5 to 7 of Gigafab 15 have been put into production,” he said.

“We have implemented active statistical process control (measurements at the control wafer site) to detect, stop and fix process variations early, such as up/down shifts in baseline measurements, variance shifts, and mismatches between tools. We have established 2D wafer profile measurement standards and monitor and compare the ‘acceptance’ profile of each wafer inline.”

“N7’s DDM reduction rate is the fastest among all nodes.”

“For automotive customers, we have implemented unique measures to achieve the demanding DPPM requirements. We will mark the good chips in the bad areas. And there will be SPC standards for marginal batches, and they will be scrapped.”

“We will support product-specific upper and lower specification standards. We will scrap wafers that exceed the specification limit or retain the entire batch of wafers for customer risk assessment.” (See the figure below. Source: TSMC)

TSMC’s different technology platforms

TSMC has developed an approach to process development and design enablement capabilities focused on four platforms – mobile, HPC, IoT and automotive. Dr. Cheng-Min Lin, Director of the Automotive Business Unit, provided an update on the platform and the unique characteristics of automotive customers.

1. Automobile Platform

Dr. Lin noted: “Automotive systems require both advanced ADAS logic technology, such as N16FFC, and advanced V2X communication RF technology. Although the CAGR for automotive is expected to be only 1.8% from now to 2022, the CAGR for semiconductor content will be 6.9%.

He continued: “L1/L2 usage will reach about 30%, with additional MCUs applied to safety, connectivity, and electric/hybrid electric vehicle functions. That’s about 30-40 MCUs per vehicle.” (His chart predicts L3/L4/L5 usage of about 0.3% in 2020 and 2.5% in 2025.)

“Digital instrument panel cockpit visualization systems will also see increased adoption, further driving semiconductor growth, from 0.2% in 2018 to 11% in 2025.”

L2+

SAE International defines the levels of support for automated driving assistance and eventually automated driving as “Level 1 to Level 5.” Perhaps in recognition of the difficulty of achieving Levels 3 to 5, a new “L2+” level has been proposed (albeit outside of SAE) with additional cameras and decision support features.

“A L2+ car will typically integrate six cameras, four short-range radar systems, and one long-range radar unit, requiring more than 50GFLOPS of graphics processing and >10K DMIPS of navigation processing throughput.”

N16FFC, then N7

The 16FFC platform has been certified for automotive environment applications, such as SPICE and aging models, basic IP features, non-volatile memory, interface IP. The N7 platform will be certified (AEC-Q100 and ASIL-B) in 2020. Dr. Lin said, "Automotive customers tend to lag behind consumer adoption by about 2~3 years to leverage DPPM learning, although this interval is shortening. We expect N7 automotive to be widely adopted in 2021."

“TSMC’s RF CMOS products will be used for SRR, LRR and LIDAR. The 16FFC-RF enhanced process will meet the requirements of automotive platforms in the second quarter of 2020.”

2. Internet of Things Platform

TSMC's IoT platform focuses on low cost, low (active) power consumption, and low leakage (standby) power consumption. Dr. Simon Wang, Director of IoT Business Development, provided the following update:

Process Roadmap

• 55ULP, 40ULP (w/RRAM): 0.75V/0.7V

• 22ULP, 22ULL: 0.6V

• 12FFC+_ULL: 0.5V (target)

• Introducing new devices for 22ULL ​​node: EHVT devices, ultra-low leakage SRAM

The 22ULL ​​SRAM is a “dual VDD rail” design with independent logic (0.6V, SVT+HVT) and bitcell VDD_min (0.8V) values ​​for optimal standby power consumption.

The 22ULL ​​node also gets an MRAM option for nonvolatile memory.

Note that a new methodology will be applied to static timing analysis for low VDD designs. Phase-based OCV (derating multiplier) cell delay calculation will transition to sign-off using free variation format (LVF). The

next generation IoT node will be 12FFC+_ULL, and risk production will start in Q2 2020. (with SVT low VDD standard cells, 0.5V VDD)

(III) Radio Frequency

TSMC emphasized its process development focus for RF technology as part of the growth in 5G and automotive applications. Dr. Jay Sun, Director of RF and Analog Business Development, highlighted the following points:

• For RF system transceivers, 22ULP/ULL-RF is the mainstream node. For higher-end applications, 16FFC-RF is suitable, followed by N7-RF in the second half of 2020.

• Significant device R&D is underway to enhance device ft and fmax at these nodes, looking forward to 16FFC-RF-Enhanced (fmax>380GHz) in 2020 and N7-RF-Enhanced in 2021.

• New top-level BEOL stacking options are available for “elevated” extra-thick metal for inductors, giving them higher Q values.

• For RF front-end designs below 6 GHz, TSMC will launch N40SOI in 2019 - transitioning from 0.18-micron SOI to 0.13-micron SOI to N40SOI, providing devices with greatly improved ft and fmax.

Performance in advanced packaging

From the seminar, it was clear that TSMC has transformed from a “pure” wafer-level foundry to a supplier of complex integrated system modules – or, according to TSMC CEO CC Wei, a leading supplier of “large-scale nano-production innovation.” This is the result of many years of R&D investment, see for example the discussion of 3D stacking in the “SoIC” section below.

Dr. Doug Yu, Vice President of Integrated Interconnect and Packaging R&D, provided a detailed update. Dr. Yu divided packaging technologies into distinct categories – “front-end” 3D chip integration (SoIC) and “back-end” packaging advances (CoWoS, InFO). In addition, he covered advances in pad pitch and Cu pillar/ SnAg bump lithography, with special mention for automotive-grade reliability requirements.

(1) Bumping technology

TSMC continues to advance bump technology, enabling 60-80um bump pitches (for smaller chips).

(2) CoWos

TSMC’s initial 2.5D packaging product is chip-on-wafer-on-substrate (CoWoS), which enables very high-performance system integration by bringing memory “closer to the processor.”

• > 50 customer products

• TSMC is developing “standardized” configurations, e.g., 1 SoC with 2 or 4 HBMs, to 2+ SoCs with 8 HBM2Es (96GB @ 2.5TB/sec)

Accordingly, TSMC will expand the maximum 2.5D interposer footprint from 1X mask (~50x50) to 3X (~85x85) with 150um bump pitch.

• Silicon interposer supports 5 metal layers and (new) deep trench capacitors – see figure below.

(3)InFo

TSMC continues to develop its Integrated FanOut (InFO) packaging products. Recall that InFO is a means of integrating (multiple) chips using a "reconstituted wafer" molding compound to provide a package substrate for RDL patterning. InFO builds on traditional small package WLCSP technology to achieve (large area) redistribution interconnects and high bump counts - see the figure below.

InFO-PoP supports stacking logic and DRAM chips on top of the base, using through-InFO-vias (TIVs) to connect the DRAM to the metal layer. The focus of InFO-PoP development is to improve the pitch and aspect ratio (vertical surface to diameter) of the TIV.

The InFO-on-Substrate product connects the (multi-chip) InFO module to the (large-area) substrate, leveraging the multiple reticle stitching technology developed for CoWoS.

(4) SoIC (“Front-End” 3D Integration)

The key announcement from the symposium on packaging was the introduction of a “front-end” 3D chip stacking topology called SoIC (System-on-Integrated Chips).

SoIC is a "bumpless" interconnect method between multiple chips. As shown in the figure below (from an early TSMC R&D paper), the Cu pads from the base die and the exposed Cu "nails" from the (thinned) top die are thermally bonded to provide electrical connections. (A suitable underfill material also exists at the die-to-die interface.)

• Through silicon vias in the chip provide connections at very tight pitches.

• Supports face-to-face and face-to-back die connections. “Known good” stacked die can be of different sizes with multiple dies on the stacking layer.

• TSMC demonstrated a physical model of a 3-high vertical SoIC stack.

• EDA support available: physical design (DRC, netlist/LVS), parasitic extraction, timing, IR/EM analysis, signal integrity/power integrity analysis, thermal/material stress analysis.

• SOIC packaged product qualification is targeted for 2019. (I understand from a separate TSMC announcement that SoIC will be in volume production in 2021.)

Summarize

A few years ago, someone half-guessed and half-jokingly said, "Only 7 customers can afford 7nm design, and only 5 customers can afford 5nm."

Obviously, the momentum of N7/N6 and N5 in mobile communications, HPC, and automotive (L1-L5) applications has dispelled this idea. TSMC is investing heavily in these nodes through DTCO, taking advantage of major advances in EUV lithography and the introduction of new materials.

In addition, we also see that in addition to traditional wafer foundry, TSMC's 2.5D and InFO "back-end" packaging products are constantly evolving, with a focus on launching tightly pitched Cu pressed full 3D stacked chips in SoIC topology. The available circuit density (mm^3) will be very attractive. However, the challenges of utilizing this technology are considerable, ranging from system architecture partitioning to complex electrical/thermal/mechanical analysis of stacked chip interfaces.

Moore's Law is definitely alive and well, even if you need 3D glasses to see it.