In-system programming technology based on LonWorks

introduction

在系统编程ISP（In System Programming）是指在用户设计的目标系统或印刷电路板上为重新配置逻辑，或实现新的功能而对器件进行编程或反复编程。

随着EDA工具的普及和ISP器件的日益成熟，ISP技术也得到了越来越广泛的应用。ISP技术的应用使得硬件设计软件化，其显著优势体现在：简化生产流程；利用同一硬件结构实现多种系统功能，使之成多功能硬件；在不特殊电路板资源的情况下进行电路板级测试；边界扫描测试；通过Modem和ISP编程接口实现对系统的远程维护和升级。

对ISP器件的编程可通过PC机进行，利用1条编程电路（或称下载电缆）将准确定时的编程信号提供给该器件。但是，这种方法不能使各种器件的数据下载脱离EDA工具独立进行，真正意义上的在系统可编程难以实现。对于ISP器件的编程也可以通过微处理器的控制程序实现，这就为基于Neuron芯片的LON网络节点提供了应用空间。

Lon(Local Operating Networks)总线是美国Echelon公司1991年推出的局部操作网络，目前已广泛应用于测控网络中。LonWorks现场总线技术在控制系统引入了网络的概念。在该技术的基础上，可以方便地实现分布式的网络控制系统，并使得控制系统更高效、更灵活、更易于维护和扩展。利用分布的智能控制节点进行在系统编程无需编程电缆，而且能够充分地利用系统资源，简化编程操作，大大拓展了在系统编程技术的应用范围。

1 基于Neuron芯片的控制节点

1.1 Neuron芯片简介

Neuron芯片的LonWorks节点的核心部分，它既能管理通道，同时具有输入/输出以及控制等能力。该芯片主要包括Neuron 3120和3150两大系列。二者的区别是3150芯片中无部ROM，但拥有访问外部存储器的接口，寻址空间可达64KB，可用于开发更为复杂的应用系统，Noeuron芯片内部固化了完整的LonTalk通信协议，确保节点间的可靠通信和互操作。芯片内部有3个8位CPU协调工作，实现Lon节点的通信和控制功能；11个编程I/O口；5个网络通信端口提供3种工作方式；单端方式、差分方式和专用方式。

1.2 控制节点的硬件结构

Lon网络节点有2种类型：基于Neuron芯片的节点（Neuron芯片是唯一的处理器）和基于主机的节点（主处理器可以是微控制器、PC机等）。一个典型的现场总线控制节点的基本结构如图1所示，主要包含以下几个部分功能块；应用 CPU 、 I/O 处理单元、通信处理器、收发器和电源。无论哪种类型的节点都有1片Neuron芯片用于通信和/或控制、1个I/O接口用于连接1个或多个I/O设备，另外还有1个收发器负责将节点连接上网。

The basic structure of the control node in this design is shown in Figure 2. The node mainly includes Neuron chip, 128KB Flash memory, 10MHz crystal oscillator, FTT-10A transceiver, I/O interface, driver, CPLD . Neuron chip has an external Flash memory expansion to store firmware and user applications. The firmware can be downloaded through the programmer, and the application can be downloaded using the programmer or the network management tool via the Lon network. In this way, the reconfiguration of the CPLD can be carried out conveniently and quickly through the Lon network. The 5 in-system programming control ispEN, MODE, SDI, SCLK Ethernet SDO occupy the 5 I/O ports of the Neuron chip. The driving capability of the Neuron chip I/O port itself is not enough. It is necessary to use 74HC367 or 74HC244 to enhance the signal driving capability, and use appropriate resistor-capacitor networks to filter the signal line to enhance the anti-interference capability.

2 Software Implementation of In-System Programming

2.1 Taking the CPLD device ispLSI of Lattic Company as an example, the E2COMS unit array that needs to be programmed in the device is shown in Figure 2.

The E2COMS components are arranged in an array in rows and columns. The address shift register indicates the current number of programming rows, and the data shift register loads the data to be written into the row. The data shift register is divided into a low-segment data register and a high-segment data register, and the data of the low and high segments are loaded separately. When programming, the data to be written to a row is first serially shifted into the data shift register, and the position corresponding to the row in the address shift register is set to 1 (the rest of the positions are set to 0), so that the row is selected, and the data in the horizontal shift register is written to the row under the action of the programming pulse. Then the address shift register is moved by 1 bit, so that the next row of the array is selected and the programming data of the next row is loaded into the horizontal register, and so on.

The JEDEC (fuse map) file is a standard format computer file for device programming information formulated by the Joint Electron Devices Engineering Council, and the programming information is represented by ASCII code. Lattice has defined a data format specifically for ISP operations, namely the ISP data stream file (ispSTREAM). The original ASCII code is represented by only 1 bit, which greatly reduces the storage space of the data file. Therefore, before executing system programming, ispCODE software is first used to implement this data conversion to form an ispSTREAM file that is easy to integrate with the Neuron C language source code.

2.2 Neuron C programming language

Neuron C is a programming language designed specifically for Neuron chips. It is derived from ANSI C and further expanded to support various operating features provided by the firmware in Neuron chips. Neuron C programming language is efficient and readable. The language adds communication, event scheduling, distributed data objects and I/O functions, and is a powerful tool for developing LonWorks applications.

In order to realize the communication between Neuron chips and I/O devices, the 11 I/O pins of Neuron chips can be defined as 34 I/O objects. Users can reasonably choose to define different I/O objects in the application according to the needs of actual applications, and then use functions such as io_in() or io_out() to implement data read and write operations on I/O objects, that is, to realize the communication between Neuron chips and I/O devices. In this design, the I/O port used as a programming signal is defined as a "bit I/O object" in the "direct I/O object". The bit input is a logic signal compatible with TTL level, and the output is CMOS level, which can drive external logic circuits compatible with CMOS and TTL.

2.3 Software Implementation

According to the internal structure of the CPLD device and its in-system programming principle, the task of the control program is to read the fuse map data from the memory, convert it into a serial data stream, and write it into the CPLD. The programming process is controlled by 5 programming signals, which are generated by pre-defined I/O ports, and then the program to read and write these I/O ports is compiled. The ISP programming process is the process of software reading and writing these ports. The key to programming is to provide accurate and timed ISP programming signals, and the timing relationship between each ISP programming signal must be guaranteed.

The overall structure of the Neuron C program is shown in Figure 4. The Neuron C source program first defines the variables, functions, and the use of I/O ports, and then writes the when() statement scheduling program. When the ISP operation needs to be performed, the relevant program is called. In Figure 4, the ispSTREAM file header includes parameters such as the CPLD device type, the pulse width of the CPLD device block erase and row programming.

Neuron C keyword allows part of the application code to be added directly to the specified memory segment. In this design, the far keyword is used to store the ispSTREAM file in the RAMFAR area. In addition, during the execution of the programming software, most hardware timing requirements (usually short) are automatically met due to the relatively long execution time of the instructions. However, the programming pulse and the total erase pulse are as long as 40ms and 200ms respectively, and there is no hardware timer on the board, so it can only be achieved by software delay.

In the NodeBuilder development environment, after executing the build command, the devicename.NEI file in the working directory is output and loaded into the programmer, and the programmer downloads the application and firmware to the Flash memory.

Conclusion

The actual operation proves that after the ISP operation of the CPLD through the Neuron chip, the CPLD realizes the predetermined function.

At present, the application of Lon network control technology in various fields such as aviation/aerospace, building control, and transportation equipment is becoming more and more mature, and because this technology has high-performance, low-cost network interface products, and it is easy to develop low-cost gateways, it realizes the organic combination of Lon network and Ethernet. Therefore, based on this experiment, the host can try to download the programming data file of the ISP device to the node of the Lon network through remote service, and the underlying field equipment can perform the in-system programming operation. In this way, the connotation and superiority of in-system programming technology can be fully reflected, and the application space of this technology can be expanded to the bottom and remote of the system. The real in-system programmable era has arrived.