HuaDa HC32A460 Series Introduction (Part 2)

虹芯侠客

HuaDa HC32A460 Series Introduction (Part 2) [Copy link]

1.4 Huada HC32A460 Series Functional Introduction

1.4.1 CPU

Huada HC32A460 series integrates a new generation of embedded ARM Cortex-M4 with FPU 32bit reduced instruction CPU, which achieves low pin count and low power consumption while providing excellent computing performance and rapid interrupt response capabilities. The on-chip integrated storage capacity can give full play to the excellent instruction efficiency of ARM Cortex-M4 with FPU. The CPU supports DSP instructions, which can realize efficient signal processing operations and complex algorithms. The single-point precision FPU (Floating Point Unit) unit can avoid instruction saturation and accelerate software development.

1.4.2 Bus Architecture (BUS)

The main system consists of a 32-bit multi-layer AHB bus matrix, which can realize the interconnection of the following host bus and slave bus.

Host Bus

Cortex-M4F core CPUI bus, CPUD bus, CPUS bus

System DMA_1 bus, system DMA_2 bus

USB DMA bus

Slave Bus

Flash ICODE bus

Flash DCODE bus

Flash MCODE bus (the bus used by hosts other than the CPU to access Flash)

SRAMH bus (SRAMH 32kB)

SRAMA bus (SRAM1 64KB)

SRAMB bus (SRAM2 64KB, SRAM3 28KB, Ret_SRAM 4KB)

APB1 peripheral bus (EMB/Timers/SPI/USART/I2S)

APB2 peripheral bus (Timers/SPI/USART/I2S)

APB3 peripheral bus (ADC/PGA/TRNG)

APB4 peripheral bus (FCM/WDT/CMP/OTS/RTC/WKTM/I2C)

AHB1 peripheral bus (KEYSCAN/INTC/DCU/GPIO/SYSC)

AHB2 peripheral bus (CAN/SDIOC)

AHB3 peripheral bus (AES/HASH/CRC/USB FS)

AHB4 peripheral bus (SDIOC)

AHB5 peripheral bus (QSPI)

With the help of bus matrix, efficient concurrent access from the host bus to the slave bus can be achieved.

1.4.3 Reset Control (RMU)

The chip is equipped with 14 reset modes.

Power-On Reset (POR)

NRST pin reset (NRST)

Brown-out reset (BOR)

Programmable Voltage Detect 1 Reset (PVD1R)

Programmable Voltage Detect 2 Reset (PVD2R)

Watchdog reset (WDTR)

Dedicated watchdog reset (SWDTR)

Power-down wake-up reset (PDRST)

Software reset (SRST)

MPU Error Reset (MPUR)

RAM Parity Reset (RAMPR)

RAMECC reset (RAMECCR)

Clock abnormal reset (CKFER)

External high-speed oscillator abnormal stop reset (XTALER)

1.4.4 Clock Control (CMU)

The clock control unit provides a range of frequency clock functions, including: an external high-speed oscillator, an external low-speed oscillator, two PLL clocks, an internal high-speed oscillator, an internal medium-speed oscillator, an internal low-speed oscillator, a SWDT-specific internal low-speed oscillator, clock prescaler, clock multiplexing and clock gating circuits. The clock control unit also provides a clock frequency measurement function (FCM). The clock frequency measurement circuit uses the measurement reference clock to monitor and measure the measured clock. An interrupt or reset occurs when it exceeds the set range. The AHB, APB and Cortex-M4 clocks are all derived from the system clock, and the source of the system clock can select 6 clock sources:

1) External high speed oscillator (XTAL)

2) External low speed oscillator (XTAL32)

3) MPLL clock (MPLL)

4) Internal High Speed Oscillator (HRC)

5) Internal medium speed oscillator (MRC)

6) Internal low speed oscillator (LRC)

The operating clock frequency of the system clock can reach 200MHz. SWDT has an independent clock source: SWDT dedicated internal low-speed oscillator (SWDTLRC). The real-time clock (RTC) uses an external low-speed oscillator or an internal low-speed oscillator as the clock source. The 48MHz clock of USB-FS and the I2S communication clock can select the system clock, MPLL, UPLL as the clock source. For each clock source, it can be turned on and off separately when not in use to reduce power consumption.

1.4.5 Power Supply Control (PWC)

The power controller is used to control the power supply, switching, and detection of multiple power domains of the chip in multiple operating modes and low power modes. The power controller consists of power control logic (PWC) and power supply voltage detection unit (PVD). The working voltage (VCC) of the chip is 1.8V to 3.6V. The voltage regulator (LDO) supplies power to the VDD domain and the VDDR domain, and the VDDR voltage regulator (RLDO) supplies power to the VDDR domain in power-down mode. The chip provides three operating modes of ultra-high speed, high speed, and ultra-low speed through the power control logic (PWC), and three low-power modes of sleep, stop, and power-down. The power supply voltage detection unit (PVD) provides functions such as power-on reset (POR), power-down reset (PDR), undervoltage reset (BOR), programmable voltage detection 1 (PVD1), and programmable voltage detection 2 (PVD2). Among them, POR, PDR, and BOR control the chip reset action by detecting the VCC voltage. PVD1 detects the VCC voltage and resets or interrupts the chip according to the register settings. PVD2 detects VCC voltage or external input detection voltage and generates reset or interrupt according to register selection. VDDR area can maintain power through RLDO after the chip enters power-down mode to ensure the real-time clock module (RTC),

The wake-up timer (WKTM) can continue to operate and maintain the data of the 4KB low-power SRAM (Ret-SRAM). The analog module is equipped with a dedicated power pin to improve the analog performance.

1.4.6 Initial Configuration (ICG)

After the chip reset is released, the hardware circuit will read the FLASH address 0x00000400H~0x0000041FH (0x00000408~0x0000041F is a reserved function address. The 24-byte address needs to be set to all 1s by the user to ensure normal operation of the chip) and load the data into the initialization configuration register. The user needs to program or erase FLASH sector 0 to modify the initialization configuration register.