Technology Foresight - Prospects for Assisted Driving Computing Power Technology Roadmap under Energy Crisis

The energy crisis caused by ADAS’ high power consumption and low efficiency

New energy vehicle heating and energy consumption issues

According to statistics from China's National Emergency Management Department, in the first quarter of 2022, a total of 640 accidents involving spontaneous combustion of smart vehicles occurred, with an average of 7 electric vehicles spontaneously igniting a day. The main reasons for electric vehicle fires are the following: battery overheating, battery aging, battery collision, high-load operation, etc. Among them, the high load operation of the battery is one of the most serious reasons.

High power consumption and low efficiency of visual algorithm computing power

As Tesla uses vision algorithms to achieve autonomous driving. Major Tier 1 manufacturers have entered an arms race in computing power. The computing power is constantly increasing, and larger computing power requires higher power consumption.

Figure 1 Vision algorithm causes power consumption issues

Multi-sensor fusion strategy for ADAS

In fact, in the field of autonomous driving, the changing area accounts for a small part of the entire image, and most of the visual data is useless data. Traditional visual processing spends a lot of energy processing these useless backgrounds, which wastes a lot of computing power and time. Using an event processing system and triggering judgment methods through time systems can increase the processing speed by 100-1000 times and reduce the amount of calculations.

Figure 2 Multi-sensor fusion technology strategy

Event cameras cannot provide depth information, and the current calculation method relying on the camera is still a simple brute force calculation. Perfect 3D perception can be achieved by using event cameras combined with lidar, millimeter wave radar, ultrasonic radar and other methods. At the same time, it can also avoid the waste of resources caused by relying on massive data and massive computing power.

ADAS domain architecture multi-sensor fusion technology

Multi-sensor synchronization problem

The image event system can solve most of the algorithms for visual recognition, but it also has some limitations. In addition to traditional image algorithms, lidar, millimeter wave radar, and ultrasonic radar are increasingly used in ADAS. As the intelligence requirements of ADAS continue to increase, autonomous driving systems need to be implemented using multiple different types of sensors for collaborative processing.

Figure 3 Multi-sensor fusion faces the challenge of time delay

Each sensor collects data and then sends it to the domain controller through the bus. There is a certain degree of delay, and the delay length of each sensor is not fixed. In order to improve the performance of deep fusion, decision planning and fusion positioning between autonomous driving sensors, the autonomous driving advanced domain controller and its associated sensors need to be time synchronized.

Commonly used time synchronization mainly includes: GPS synchronization, SyncE, NTP and PTP (IEEE 1588) time synchronization. For ADAS, the time-sensitive network TSN (Time Sensitive Network) technology is mainly used.

Figure 4 Principle of time-sensitive network technology TSN

TSN originally originated from the application requirements of Ethernet AVB in the audio and video field, and was used to solve the requirements for high bandwidth, high real-time performance, and high transmission quality of audio and video networks. The core principle of TSN is based on time traffic scheduling and management, which is implemented through the scheduling of the time-aware shaper TAS (Time Aware Shaper) in the TSN network.

Figure 5 Using phase-locked loop technology to achieve clock frequency phase locking

TSN can calculate the transmission line delay problem more accurately. However, if the master and slave devices use their own independent clocks, there will still be a frequency offset problem, which requires the use of a very high-precision crystal oscillator to implement the transmission function. Based on comprehensive considerations such as cost, OCXO/VCXO+PLL is usually used to achieve frequency locking of the slave device clock and achieve frequency synchronization with the master clock.

In ADAS applications, TSN combined with OCXO + phase-locked loop can be used to achieve time synchronization between each sensing unit and GPU/FPGA, eliminate accumulated errors, and achieve unification of clock sources and complete integration of multiple sensors.

Sensor high-speed data exchange issues

The image event system contains massive data. To meet the deep fusion of multi-sensors, these data must complete information exchange in a very short time. Inspired by streamlined processors, processor-independent 32-bit or 64-bit local buses have been used. The bus's highest operating frequency is 33MHz/66MHz, with a peak speed of 533MB/s. This bus is called the Peripheral Interconnect Standard bus (PCI bus).

Figure 6 PCI bus architecture block diagram

Later, based on the PCI bus, the PCI-X bus protocol was derived, with its operating frequency increased to 133MHz and its peak bandwidth reaching 1064MB/s. Later, it developed to PCI-X 2.0.

After the PCI bus developed to PCI-X 2.0, it was difficult to further improve the transmission rate. This is because the parasitic inductance of the transmission line between the clock and data signals forms crosstalk, which seriously affects the waveform of the data signal. It is easy to misjudge the sampling signal and affect the communication efficiency.

Figure 7 Inter-symbol interference caused by high-speed digital signals

When digital signals are transmitted at high speed, it is easy to produce antenna effects, radiate to the surroundings, produce electromagnetic induction, and form inter-code interference. Inter-code interference includes the source signal and the interfered signal. This leads to the continuous improvement of the transmission signal decision threshold. In order to improve the resistance to inter-symbol interference, someone proposed to use a differential transmission model.

Figure 8 Differential signals eliminate inter-symbol interference

This differential signal transmission method later developed into the USB and PCIe transmission buses through a series of evolutions and improvements. The PCIe bus has undergone iterations and has now evolved to PCIe5.0. According to the latest news, PCIe has just released PCIe6. 0 and PCIe7.0 specifications.

Figure 9 PCIe bus technology improves transmission rate

Comparison of power consumption of computing power of different technologies

Dynamic power consumption based on SRAM technology

Currently, most visual algorithm processing systems on the market are implemented based on GPUs and FPGAs, and most of these processors are based on static random access memory technology as the core unit.

Figure 10 Internal structure of SRAM cell

The SRAM unit is composed of six N-channel CMOS tubes, four of which form the basic RS flip-flop for memorizing binary codes, and the other two are used as gate switches to control the flip-flops and bit lines.

Figure 11 SRAM architecture dynamic power consumption

Because the upper and lower tubes of SRAM are working in a deeply saturated state. Therefore, when the CMOS inverter changes from one stable working state to another stable working state, the upper and lower tubes will be turned on at the same time. At this time, the internal resistance of CMOS is very small, and the corresponding current will be very large. Therefore, the dynamic power consumption generated will be very large.

Dynamic power consumption based on Flash technology

In addition to CMOS-based SRAM processors, Excelpoint engineer Wolfe Yu introduced a Flash architecture FPGA processor based on stacked gate MOS launched by Microchip.

Figure 12 The difference between Flash architecture FPGA and SRAM architecture FPGA

One of the biggest features of Flash architecture FPGA is that the operating point is static, and there will be no large current fluctuations during dynamic switching, which can save up to 50% of power loss. Wolfe said that Microchip's latest PolarFire can achieve 2.6 times the GOPS/W computing power compared to similar 28nm devices.

Microchip’s turnkey solution based on ADAS technology

Driven by factors such as policies, Internet cross-border competition, and consumers' internal needs, ADAS penetration will increase rapidly. Some low-end models are also beginning to be equipped with some ADAS functions to enhance their selling points.

Microchip based time sensitive networking solutions

Microchip launches LAN937X series of TSN switching devices. As the industry's most functional switching solution that complies with the IEEE 802.1AS standard, it enables lower latency data traffic and higher clock accuracy. In the next step, Microchip will also launch the LAN969X series of products integrating 1000 BASE TI PHY.

TSN can achieve network transmission delay. However, due to frequency offset differences in clock crystals, frequency errors between different nodes may occur. In order to solve the frequency offset problem, people usually use PLL phase-locked loops and VCXO to lock the clock in the nodes. frequency. At the same time, in order to further synchronize the 1PPS clock of the GPS, the 1PPS clock also needs to be synchronized. Microchip's ZL307XX series integrates 5 PLLs and supports 1PPS and SYNCE. Meets most Ethernet time synchronization requirements. Currently, Microchip has cooperated with some car companies and began to evaluate Microchip’s clock solutions.

Figure 13 Microchip TSN solution

LAN93XX is paired with 1000BASE-T1 PHY LAN887X and synchronous digital phase-locked loop ZL307XX for precise timing of IEEE 1588v2 and IEEE 802.1AS-2020, used for multi-sensor time synchronization, compliant with IEEE P802.1Qci, IEEE P802.1Qav, etc., and can meet ADAS Real-time networking requirements. For the low-end market, Microchip's LAN937X, combined with the 100BASE-T1 LAN8770, can also meet customer needs.