IP core design of asynchronous serial communication interface

Abstract: The asynchronous serial communication interface (SCI) is widely used in the design of various MCU, DSP and MPU chips because of its simple structure and easy use. This article gives a general method for the structure design of an asynchronous serial communication interface IP core with the state machine as the control core and the data flow as the execution center. This method has been verified in the DSP chip designed by the author. Keywords: SCI IP core design state machine data flow Introduction At present, microelectronic application system design technology based on traditional IC chips is shifting to system-on-chip (SoC, System on Chip) technology development based on intellectual property (IP, Intellectual Property) cores. In addition, IC design is developing rapidly in China, and IC design centers and companies of various sizes continue to appear. Therefore, the design of IP cores has gradually become a supporting technology for domestic microelectronic system design. There are two major categories of IP cores from the perspective of application functions: microprocessor IP cores (such as 8-bit 8051 core, 32-bit ARM core, etc.) and various interface IP cores (such as LCD controllers, various serial bus interface IP cores) wait). This article takes the structural design of the asynchronous serial communication interface (SCI, Serial Communication Interface) interface IP core as an example to explain the design method of interface IP cores such as SCI, UART, SPI, and USB. SCI's communication method uses the standard NRZ format for asynchronous digital communication between peripherals. Because of its simple structure, it is usually embedded into DSP, MCU and MPU or peripheral control chips as an interface function module of the chip. SCI usually consists of three functional units: baud rate pulse generation unit, sending unit and receiving unit. Its structure is shown in Figure 1. In SCI data transmission and reception, the data format of the data frame is much more complex than the data format of the address frame. Under different communication methods, the formats of data frames are different. To this end, state machines corresponding to the data frame format are introduced in the transmitter and receiver to realize data flow control. What this article introduces is a general design method based on this design idea. 1 SCI data sending unit The main function of the data sending unit is to complete the parallel/serial conversion and sending of data, and at the same time generate a sending flag. Its structure is shown in Figure 2, and the character sending state machine is shown in Figure 3. The following briefly introduces each functional module of the sending unit and its state transition. (1) The TXD clock frequency divider divides the clock by eight based on the baud rate and outputs two basic pulses—TXD_CLK_WORK (used for counting, shifting, etc.) and TXD_CLK_END (used for flag bit generation and data stream output) ). (2) The TXD status register sets the two control bits of the communication control register 2 - the TXEMPTY and TXRDY bits through this status register to indicate that data is written to SCI_TXBUF and the sending process is started. (3) Sending character counter When the output status of the character state machine is to allow character counting, it starts counting the sent characters. When the counter value is equal to the programmed number of characters, the TX_CHAP_REACH signal is output as a character state machine stimulus, causing it to enter a non-character output state. (4) Sending idle line counter When the character state machine enters the sending idle line data state, it starts working. When the count reaches a certain value, the output signal TX_IDLECOUT_REACH is used as a character state machine stimulus to enter the non-idle line data counting state. (5) The formation of the sending data stream is under the action of the high-level pulse of TXBUF2SHIFT. The data to be sent in SCI_TXBUF is selected by the selector to send the specified number of bits to the low bits of SCI_TXSHIFT, and the insufficient high bits are cleared to "0". At the same time, the TXWAKE data is also sent to the WUT register. In the address bit mode, the address bit is formed in the WUT under the control of ADDR_IDLE; and the parity bit is formed by the logical OR of the SCI_TXSHIFT data bit, address bit and parity mode bit. . (6) The current sending character state machine realizes the output and conversion of the sending character state under the stimulation of startup, control bit, counter overflow, etc. The incentives for the transmit character state machine are: TXEMPTY (start TXD transmission when "0"), ADDR_IDLE (address/idle line mode selection bit), PARENA (parity check enable bit), STOPBIT (select 1 or 2 stop bits) ), WUT (send idle bit data enable bit), TX_CHARCOUT_REACH (send enough characters), TX_IDLECOUT_REACH (send enough idle bits). The states of the sending character state machine (see Figure 3) are: 1 is the frame stop bit (1 bit), 3 is the frame's first stop bit (2 bits), 5 is the frame's second stop bit (2 bits), 8-bit frame Start bit, 9 is standby state, A is frame data bit, B is idle line mode start bit, C is frame address bit, E is frame parity bit, F is idle line mode stop bit, D is idle line Mode count 0~7. 2 SCI data receiving unit The function of the data receiving unit is to complete the reception of serial data and the generation of reception flag bits. Its structure is shown in Figure 4, and the receiving start bit detection and receiving character state machines are shown in Figures 5 and 6. The functional modules and state transitions of the receiving unit are described below. (1) The RXD clock divider by eight divides the baud rate clock by eight and keeps it synchronized with the characters of the received serial data stream. It outputs two clock pulses: RXD_CLK_WORK, used for counting, shifting, etc.; RXD_CLK_END, which provides pulses within the byte period before the stop bit in various modes of data flow. Figure 4 SCI digital receiving unit (2) start bit detection module is a three-digit four-state machine. There are two excitations: RXD_1_VALUE—received serial data stream excitation; RXD_END_CHK—pulse excitation after a reception. Its states are as follows (see Figure 5): 0 (standby state), 1 (empty state), 2 (empty state), 3 (finding the transition state from "1" to "0"), 4 (output clock Synchronization signal), 5 (RXD_CLK_AYN and RXD_START_DRV are output during character reception). (3) The main function of the character detection module is to receive data streams. The data flows through three registers driven by the sampling clock. Then, under the action of the RXD_CLK_WORK pulse, the data in the three registers pass through the voting circuit and send the data to the receive data buffer RXD_VALUE. In order to send the data to the shift register RX_SHIFT Prepare. (4) The current received character state machine is used to identify which character the currently received data is and which state it will transition to in the next RXD_CLK_WORK character cycle. It also drives other components to perform appropriate operations based on the current received character state. operate. Its incentives include: RXD_START_DRV (RXD start bit valid incentive), RX_CHAR_REACH (the number of RXD characters received is enough), CCR3_ADDR_IDLE (address/idle line mode selection), CCR5_PARENA (parity check enable). Its states (see Figure 6) are: 0 (standby state), 1 (frame data bit), 2 (frame start bit), 3 (frame address bit), 4 (frame parity bit), 5 (empty state) ), 6 (frame stop bit). (5) Receive character counter When the receive character state machine is in the frame data bit stage, it starts counting; when it is the same as the programmable data, RX_CHAR_REACH is output to the receive character state machine. (6) Receive idle line counter When in the standby state, the counter is started. When the count reaches a certain value, a pulse is output and RXSP1_RXWAKE is set to 1; when the next character is about to be received, the SCI_RXBUF register is read or the SCI is reset, RXST1_RXWAKE is reset to 0. (7) Receive data shift register (SCI_RXSHIFT) Receives and detects the serial data stream according to the status of the receiving character state machine, sends the received correct data to SCI_RXBUF and sets the corresponding flag, otherwise the error flag is set. (8) The BRKDT discontinuity detection counter starts working when an RXST4_FE frame error occurs. When RXD_VALUE is "1", it is reset; when RXD_VALUE is "0", it means no data is received and counting starts; when it reaches a certain value, the full count signal is output, and the interrupt detection flag RXST5_BRKDT is set at this time. Conclusion In summary, in the design of various serial interface IP cores, the internal unit structure can be divided into two parts: control and execution. Among them, the design of the control logic uses a unipolar or multi-level state machine as the core, and cooperates with the structural design of its various excitation units to achieve a clear structure and realize more complex logic; the design of the actuator uses a control The status of the logical output is used as the center to design a data selector or data distributor, which can realize the complex flow direction of the data flow (please see the online supplementary version: www.dpj.com.cn).