Design of Inland River Navigational Aid Monitoring System Based on Nios II Soft-core

Abstract: The design method of the inland navigation mark monitoring system based on NiosⅡ soft core and the VHDL design of AD7862 control circuit are described. From the perspective of the system, a complete design scheme of the navigation mark monitoring system is proposed, and the hardware design block diagram of the navigation mark monitoring terminal based on Nios II is given, and the simulation results in Modesim are obtained. According to the on-site operation, the system can monitor the working status of the navigation mark in real time, achieve industrial-level quality assurance of the system, and has the advantages of high reliability, high real-time and convenient maintenance.
Keywords Nios II; SOPC builder; FPGA; navigation mark monitoring system

Inland waterway transportation is an important part of the national comprehensive transportation system and the comprehensive utilization of water resources, and is an important strategic resource for achieving sustainable economic and social development. Navigation marks are the basic navigation aids for inland waterways. The traditional navigation mark management model is backward, with low standardization, poor real-time and safety performance, and can no longer meet the needs of high-quality and safe navigation proposed by the increasingly busy waterway transportation.
Nios II is a soft-core CPU based on RISC technology launched by Altera. As a 32-bit bus embedded system microprocessor soft core that users can configure and build at will, its hardware design is user-customizable and has the advantages of flexibility and scalability.
Combined with the actual situation of inland waterway navigation mark management, a new design scheme of navigation mark monitoring system based on Nios II soft core is introduced. According to the operation results of the system, the design realizes the expected functions of the system, so that the monitoring center can monitor the working parameters and status of the navigation mark in real time, manage information, and find faults in time, thereby improving the reliability of the navigation mark, enhancing the safety of waterway navigation, and improving management efficiency.

1 Implementation of system terminal hardware circuit
The terminal hardware design of the navigation mark monitoring system mainly includes peripheral devices composed of GSM short message sending module, GPS data acquisition module, collision pressure processing circuit, etc., and core logic with 32-bit Nios II CORE as the main body. The system terminal hardware block diagram is shown in Figure 1.

1.1 Peripheral devices
Peripheral devices refer to some specific control circuits or module interfaces, which are non-logical and cannot be implemented with programmable logic in FPGA/CPLD.
1.1.1 Collision pressure processing circuit
Real-time monitoring is required to determine whether the navigation mark is hit, to avoid damage to the navigation mark due to collision, which may result in failure to provide correct instructions to the navigation body. According to the system design requirements, the circuit design for measuring the collision pressure signal is shown in Figure 2.

The force sensor sampling data is sent to the two-stage operational amplifier LM324 for adjustment and amplification, and then sent to VA1 and VA2 of the dual 12-bit A/D converter. AD7862 samples 4 channels at a sampling rate of 250 kHz at the same time. The signal input to the on-chip sample-and-hold amplifier is differentiated and held during the ADC input period, converting the analog signal into the digital signal required by the system.
1.1.2 GSM and GPS modules
The control center GSM Modem uses Siemens' wireless communication engine TC35 terminal, which consists of an engine module, an antenna and its peripheral circuits. The user port of the monitoring terminal TC35i module uses a 40-pin ZIP socket, which includes analog audio, RS232 interface, SIM card interface and power supply. The peripheral circuits are mainly SIM card circuits and startup control circuits.
The GPS data acquisition module uses a high-performance, low-power small GPS receiver B12 OEM from Thales Navigation (Thales Navigation) of the United States. Through unique software algorithms and the latest GPS technology, Thales optimizes B12 into a handheld product for fast processing, navigation, vehicle tracking, mobile data, and telematics. It supports differential remote operation and can improve the system differential positioning accuracy.
1.2 Design of on-chip logic
The process of converting the conceptual structure into a data model corresponding to the actual system is called logic structure design. The on-chip logic design of FPGA includes system modules and user-defined logic areas. System modules refer to the designs automatically generated by SOPC builder, which will generate corresponding HDL description files based on the IP selected by the user. The user-defined logic area can contain user-defined Avalon peripherals and other user-defined logic that is not related to the system module.
The programmable logic resources in FPGA and existing IP soft cores, such as Nios II core, on-chip Boot ROM, on-chip dual-port RAM for FIFO, timer Timer, JTAG UART, etc., are used to form the interface function module of the embedded system processor.
1.2.1 Serial communication interface UART
UART is a serial communication interface based on RS232 communication protocol, which is used to implement simple RS232 asynchronous transmission and reception logic in Altera's FPGA. Because the data communication interfaces of both GSM and GPS modules are standard RS232 serial interfaces, they can be easily connected to the serial port of the NiosⅡ system.
In the hardware design block diagram of the monitoring terminal shown in Figure 1, UART-1 is connected to the GSM short message sending module TC35i, and AT commands are used to control TC35i to send and receive information and dial. During control, it communicates with the GSM TC35 Modem through the RS232 serial port. The GSM module is connected to the GSM network and transmits the working parameters and status information of the beacon in the form of text messages according to the prescribed communication protocol.
UART-2 is connected to the GPS OEM board, and receives the navigation signal through the receiving antenna of the GPS positioning module. After demodulation and processing by the receiver, the location information of the beacon light is obtained, including the code of the beacon light, the longitude and latitude of the location, the measurement time and other information, and then the longitude and latitude coordinates are transmitted to the monitoring center through the wireless communication system.

1.2.2 Customized AD7862 interface VHDL design
Nios II is a flexibly customizable CPU, and its peripherals are optional IP soft cores or custom logic. By customizing the VHDL code of the AD7862 interface, write its user logic as a system peripheral. Part of the VHDL code is as follows

For this control circuit design, the simulation using Modesim is shown in Figure 3. Through analysis, the design meets the timing requirements.

2 Implementation of system terminal software design
After using SOPC Builder development tools to create the hardware of the dedicated processor system, SOPC Builder also provides a Nios II integrated development environment IDE for writing software codes to operate these on-chip hardware. This software development environment includes language header files, peripheral interface drivers, and the kernel of the real-time operating system. It can complete the editing, compiling, debugging, and downloading of the entire software project, improving the efficiency of software development. The
main control program realizes automatic alarm, status query, location display, and other functions by collecting data. The system performs power-on reset on GSM, sets the area information of the four coordinate points of the beacon light, sets the working time intervals of four GPS, and detects whether other system parameters of the beacon light need to be restarted. The program flow is shown in Figure 4.

3 Conclusion This paper
introduces the design of an inland navigation mark monitoring system based on the Nios II soft-core processor. Compared with the traditional and limited hardware organization and connection control system solution, the powerful logic control of FPGA combined with the flexible functions of the Nios II soft core can easily realize function modification and addition; the high degree of integration capability can greatly reduce the product volume and the interference of external signals on the system, and increase the reliability, stability and flexibility of the system. The wireless transmission system using GSM and GPS for positioning data is simple, stable, reliable, and has a wide coverage, and has a great advantage in cost.